Rainbow Electronics MAX8649 - Manual (Page 10)

MAX8649
1.8A Step-Down Regulator with Differential
Remote Sense in 2mm x 2mm WLP
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Pin Description
PIN NAME FUNCTION
A1 IN1
Anal og S up p l y V ol tag e Inp ut. The i np ut vol tag e r ang e i s 2.5V to 5.5V . Place an 11 Ω resistor between
IN1 and the input supply. Bypass the input supply with a 2.2µF ceramic capacitor as close as
possible to the 11
Ω resistor. Byp ass IN 1 to the 2.2µF cap aci tor g r ound p l ane ter m i nal w i th a 0.1µF
cer am i c cap aci tor as cl ose as p ossi b l e to the IC . C onnect IN 1 and IN 2 to the sam e p ow er sour ce.
A2 AGND Analog Ground. Connect AGND to the PCB ground plane.
A3 VID1
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
A4 IN2
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 10µF and 0.1µF ceramic capacitors
as close as possible to the IC. Connect IN1 and IN2 to the same power source.
B1 SNS+ Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.
B2 EN
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.
B3, B4 LX
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel
MOSFETs. LX is high impedance during shutdown.
C1 SNS- Output Voltage Remote Sense, Negative Input. Connect to a quiet ground directly at the load.
C2 VID0
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
C3, C4 PGND Power Ground. Connect both PGND bumps to the PCB ground plane.
D1 V DD
Logic Input Supply Voltage. Connect V DD to the logic supply driving SDA, SCL, and SYNC. Bypass
V DD to AGND with a 0.1µF ceramic capacitor. When V DD drops below the UVLO threshold, the I 2 C
registers are reset, but the EN control is still active in this mode.
D2 SDA I 2 C D ata Inp ut. D ata i s r ead on the r i si ng ed g e of S C L and d ata i s cl ocked out on the fal l i ng ed g e of S C L.
D3 SCL I 2 C Clock Input
D4 SYNC
E xter nal C l ock S ynchr oni zati on Inp ut. C onnect S Y N C to a 13M H z, 19.2M H z, or 26M H z system cl ock.
The D C - D C r eg ul ator can b e for ced to synchr oni ze to thi s exter nal cl ock d ep end i ng on I
2 C setti ng . S ee
Tab l e 8. S Y N C d oes not have an i nter nal p ul l d ow n. C onnect S Y N C to AG N D i f not used .