Rainbow Electronics MAX17117 - Manual (Page 21)

Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
MAX17117
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case where the supply voltage is 8.5V and the output
voltage is 4.25V with an output source current of 30mA,
the power dissipated is 128mW.
LDO
The power dissipated in the LDO depends on the LDO’s
output current, input voltage, and output voltage:
( )
LDO LDOO IN LDOO
PD I V V = × −
Scan-Driver Outputs
The power dissipated by the six CKH_ scan-driver out-
puts depends on the scan frequency, the capacitive load
on each output, and the difference between the GHON
and VGL supply voltages:
( ) 2
SCAN SCAN PANEL GHON VGL
PD 6 f C V V = Ч Ч Ч −
If the scan frequency is 50kHz, the load of the six CKH_
outputs is 3.4nF, and the supply voltage difference is
30V, then the power dissipated is 0.92W.
PCB Layout and Grounding
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
• Minimize the area of high-current loops by placing the
inductor, output diode, and output capacitors near the
input capacitors and near LX and PGND. The high-
current input loop goes from the positive terminal of
the input capacitor to the inductor, to the IC’s LX pin,
out of PGND, and to the input capacitor’s negative ter-
minal. The high-current output loop is from the positive
terminal of the input capacitor to the inductor, to the
output diode (D1), to the positive terminal of the output
capacitors, reconnecting between the output capaci-
tor and input capacitor ground terminals. Connect
these loop components with short, wide connections.
Avoid using vias in the high-current paths. If vias are
unavoidable, use many vias in parallel to reduce resis-
tance and inductance.
• Create a power ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all these
together with short, wide traces or a small ground
plane. Maximizing the width of the power ground trac-
es improves efficiency and reduces output-voltage
ripple and noise spikes. Create an analog ground
plane (AGND) consisting of all the feedback-divider
ground connections; the operational-amplifier-divid-
er ground connection; the OPAS bypass capacitor
ground connection; the COMP, SS, and SET capaci-
tor ground connections; and the device’s exposed
backside pad. Connect the AGND and PGND islands
by connecting the PGND pin directly to the exposed
backside pad. Make no other connections between
these separate ground planes.
• Place the feedback voltage-divider resistors as close
as possible to their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes the feedback trace to
become an antenna that can pick up switching noise.
Care should be taken to avoid running the feedback
trace near LX or the switching nodes in the charge
pumps.
• Place the IN pin bypass capacitor as close as pos-
sible to the device. The ground connections of the
IN bypass capacitor should be connected directly to
AGND at the backside pad of the IC.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load for
best transient responses.
• Minimize the size of the LX node while keeping it wide
and short. Keep the LX node away from the feedback
node and analog ground. Use DC traces as a shield
if necessary.
Refer to the MAX17117 Evaluation Kit for an example of
proper board layout.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to
www.maxim-ic.com/packages . Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
32 TQFN-EP T3255N+1 21-0140