Rainbow Electronics MAX15022 User Manual
Page 16
MAX15022
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
16
______________________________________________________________________________________
Use the following equation to calculate the input ripple
when only one regulator is enabled:
The MAX15022 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use additional
bulk capacitance if the input source impedance is high. If
using a lower input voltage, additional input capacitance
helps to avoid possible undershoot below the undervolt-
age lockout threshold during transient loading.
Output-Capacitor Selection
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of
ΔV
Q
(caused by
the capacitor discharge) and
ΔV
ESR
(caused by the
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
where
ΔI
P-P
is the peak-to-peak inductor current, and
f
SW
is the switching frequency.
ΔV
ESR
and
ΔV
Q
are not directly additive since they are
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR,
ΔV
Q
dominates. If
using electrolytic capacitors,
ΔV
ESR
dominates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with an
increased duty cycle. The response time (t
RESPONSE
)
depends on the gain bandwidth of the controller (see
the
Compensation-Design Guidelines
section). The
resistive drop across the output capacitor’s ESR
(
ΔV
ESR
), the drop across the capacitor’s ESL (
ΔV
ESL
),
and the capacitor discharge (
ΔV
Q
) causes a voltage
droop during the load-step (I
STEP
). Use a combination
of low-ESR tantalum/aluminum electrolyte and ceramic
capacitors for better load transient and voltage ripple
performance. Non-leaded capacitors and capacitors in
parallel help reduce the ESL. Keep the maximum out-
put-voltage deviation below the tolerable limits of the
electronics being powered.
Use the following equations to calculate the required
output capacitance, ESR, and ESL for minimal output
deviation during a load step:
where I
STEP
is the load step, t
STEP
is the rise time of the
load step, and t
RESPONSE
is the response time of the
controller.
Compensation Design Guidelines
The MAX15022 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by
comparing the output voltage against a fixed reference.
The subsequent “error” voltage that appears at the
error-amplifier output (COMP_) is compared against an
internal ramp voltage to generate the required duty
cycle of the PWM. A second order lowpass LC filter
removes the switching harmonics and passes the DC
component of the PWM signal to the output. The LC fil-
ter has an attenuation slope of -40dB/decade and intro-
duces 180° of phase shift at frequencies above the LC
resonant frequency. This phase shift in addition to the
inherent 180° of phase shift of the regulator’s negative
feedback system turns the feedback into unstable posi-
tive feedback. The error amplifier and its associated
circuitry must be designed to achieve a stable closed-
loop system.
The basic controller loop consists of a power modulator
(comprised of the regulator’s PWM, associated circuitry,
and LC filter), an output feedback divider, and an error
amplifier. The power modulator has a DC gain set by
V
AVIN
/V
RAMP
where the ramp voltage (V
RAMP
) is a func-
tion of the V
AVIN
and results in a fixed DC gain of 4V/V,
providing effective feed-forward compensation of input-
voltage supply DC variations. The feed-forward com-
pensation eliminates the dependency of the power mod-
ulator’s gain on the input voltage such that the feedback
compensation of the error amplifier requires no modifi-
cations for nominal input-voltage changes. The output
filter is effectively modeled as a double-pole and a sin-
gle zero set by the output inductance (L), the DC resis-
tance of the inductor (DCR), the output capacitance
(C
OUT
), and its equivalent series resistance (ESR).
ESR m
V
[mV]
I
[A]
C
I
[A] t
V [V]
ESL
V
[mV] t
I
[A]
ESR
STEP
OUT
STEP
RESPONSE
Q
ESL
STEP
STEP
[
]
[
]
[
]
[
]
[
]
Ω
Δ
Δ
Δ
=
=
Ч
=
Ч
μ
μ
μ
F
s
nH
s
C
F
I
[A]
8
V [V] f
[MHz]
ESR m
2
V
[mV]
I
[A]
OUT
P P
Q
SW
ESR
P P
[
]
[
]
μ =
Ч
Ч
=
Ч
−
−
Δ
Δ
Ω
Δ
Δ
I
[A]
I
[A]
V
[V]
V
V
[V]
V
[V]
CIN(RMS)
LOAD(MAX)
OUT_
PVIN_
OUT_
PVIN_
=
Ч
Ч
−
(
)