Rainbow Electronics HT24LC16 - Manual (Page 3)

Symbol Parameter Remark
Standard Mode* V
CC
=5V ±10%
Unit
Min. Max. Min. Max.
t
AA
Output Valid from Clock ¾ ¾ 3500 ¾ 900 ns
t
BUF Bus Free Time
Time in which the bus must be
free before a new transmis-
sion can start
4700 ¾ 1200 ¾ ns
t
SP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time ¾ 100 ¾ 50 ns
t
WR Write Cycle Time ¾ ¾ 5 ¾ 5 ms
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
=2.2V to 5.5V
For relative timing, refer to timing diagrams
HT24LC16
Rev. 1.20 3 November 4, 2002
Functional Description
· Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
· A0, A1, A2
The HT24LC16 does not use the device address pins
which limits the number of devices on a single bus to
one. The A0, A1 and A2 pins have no connection.
· Write protect (WP)
The HT24LC16 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
V
CC
, the write protection feature is enabled and oper-
ates as shown in the following table.
WP Pin Status Protect Array
At V
CC
Full Array (16K)
At V
SS
Normal Read/Write Operations
Memory organization
Internally organized with 2048 8-bit words, the 16K re-
quires an 11-bit data word address for random word ad-
dressing.
Device operations
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
Device addressing
The 16K EEPROM devices require an 8-bit device ad-
dress word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The 16K does not use any device address bits but in-
stead the 3 bits are used for memory page addressing.
These page addressing bits on the 16K devices should
be considered the most significant bits of the data word
address which follows. The A0, A1 and A2 pins have no
connection.
S C L
S D A
D a t a a l l o w e d
t o c h a n g e
A d d r e s s o r
a c k n o w l e d g e
v a l i d
S t o p
c o n d i t i o n
S t a r t
c o n d i t i o n