Rainbow Electronics HT24LC16 - Manual (Page 4)

HT24LC16
Rev. 1.20 4 November 4, 2002
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Write operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
· Page write
The 16K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop con-
dition after the first data word is clocked in. Instead, af-
ter the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
z e r o a f t e r e a c h d a t a w o r d r e c e i v e d . T h e
microcontroller must terminate the page write sequence
with a stop condition (refer to Page write timing).
The data word address lower four bits are internally in-
cremented following the receipt of each data word.
The higher data word address bits are not incre-
mented, retaining the memory page row location.
· Acknowledge polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W=0). If the device is still busy
with the write cycle, then no ACK will be returned. If
the cycle is completed, then the device will return the
ACK and the master can then proceed with the next
read or write command.
R / W 1 0 A 2 A 1 A 0
D e v i c e A d d r e s s
1 0
R / W
A 2 A 1 A 0 S P
D e v i c e a d d r e s s W o r d a d d r e s s D A T A
A C K
S t o p
S t a r t
S D A
A C K A C K
Byte write timing
P
D e v i c e a d d r e s s W o r d a d d r e s s D A T A n
A C K
S t o p
S t a r t
S D A
A C K A C K
S
A C K
D A T A n + 1 D A T A n + x
Page write timing
S e n d W r i t e C o m m a n d
S e n d S t o p C o n d i t i o n
t o I n i t i a t e W r i t e C y c l e
S e n d S t a r t
S e n d C o n t r o l B y t e
w i t h R / W = 0
( A C K = 0 ) ?
N e x t O p e r a t i o n
N o
Y e s
Acknowledge polling flow