Rainbow Electronics ATmega162V - Manual (Page 144)

144
ATmega162/V
2513E–AVR–09/03
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to MAX then
restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOT-
TOM. In inverting Compare Output mode, the output is set on Compare Match and
cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-
slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 64. The TCNT2 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2
slopes represent compare matches between OCR2 and TCNT2.
Figure 64. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag ( TOV2 ) is set each time the counter reaches MAX. If
the interrupt is enabled, the interrupt handler routine can be used for updating the com-
pare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2
pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM21:0 to three (See Table 62 on page
150). The actual OC2 value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the
OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or set-
ting) the OC2 Register at the timer clock cycle the counter is cleared (changes from
MAX to BOTTOM).
TCNTn
OCRn Update and
TOVn Interrupt Flag Set
1 Period 2 3
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Interrupt Flag Set
4 5 6 7