Rainbow Electronics AT45DB642 - Manual (Page 5)

5
AT45DB642
1638F–DFLSH–09/02
As with the Continuous Array Read, the CS pin must remain low during the loading of the
opcode, the address bytes, the don't care bytes, and the reading of data. During a Burst Array
Read with Synchronous Delay, when the end of a page in main memory is reached (the last bit
or the last byte of the page has been clocked out), the system must send an additional 32
don't care clock cycles before the first bit (or byte if using the parallel interface mode) of the
next page can be read out. These 32 don't care clock cycles are necessary to allow the device
enough time to cross over the burst read boundary (the crossover from the end of one page to
the beginning of the next page). By utilizing the 32 don't care clock cycles, the system does
not need to delay the SCK/CLK signal to the device which allows synchronous operation when
reading multiple pages of the memory array. Please see the detailed read timing waveforms
for illustrations (beginning on page 21) on which clock cycle data will actually begin to be
output.
When the last bit (or byte in the parallel interface mode) in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. The
transition from the last bit (or byte when using the parallel interface) of the array back to the
beginning of the array is also considered a burst read boundary. Therefore, the system must
send 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode)
of the memory array can be read.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Burst Array Read
with Synchronous Delay is defined by the f
BARSD
specification. The Burst Array Read with Syn-
chronous Delay bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H
or D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and a series of don’t care bytes (four don’t care bytes
if using the serial interface or 60 don’t care bytes if the using parallel interface). The first 13
bits (PA12 - PA0) of the 24-bit (three-byte) address sequence specify the page in main mem-
ory to be read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the
starting byte address within that page. The four or 60 don’t care bytes that follow the three
address bytes are sent to initialize the read operation. Following the don’t care bytes, addi-
tional pulses on SCK/CLK result in data being output on either the SO (serial output) pin or the
parallel output pins (I/O7 - I/O0). The CS pin must remain low during the loading of the
opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a
page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-
state the output pins (SO or I/O7 - I/O0).
BUFFER READ: Data can be read from either one of the two buffers, using different opcodes
to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer
1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a buffer read,
the opcode must be clocked into the device followed by three address bytes comprised of 13
don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the three address bytes,
an additional don’t care byte must be clocked in to initialize the read operation. Since the
buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to
be read from the buffer. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high
transition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0).