Rainbow Electronics ATF1516ASL - Manual (Page 5)

ATF1516AS(L)
5
Programmable Pin-keeper Option
for Inputs and I/Os
The ATF1516AS offers the option of programming all input
and I/O pins so that “pin keeper” circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Input Diagram
I/O Diagram
Speed/Power Management
The ATF1516AS has several built-in speed and power
management features. The ATF1516AS contains circuitry
that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides proportional power savings for most applica-
tions running at system speeds below 50 MHz.
To further reduce power, each ATF1516AS macrocell has
a reduced-power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1516AS also have an optional power-down mode.
In this mode, current drops to below 10 mA. When the
power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power-
down option is selected in the design source file. When
enabled, the device goes into power-down when either
PD1 or PD2 is high. In the power-down mode, all internal
logic signals are latched and held, as are any enabled
outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power-down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate
buried foldback and cascade logic signals.
All power-down AC characteristic parameters are com-
puted from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder,
t
RPA
, must be added to the AC parameters, which include
the data paths t
LAD
, t
LAC
, t
IC
, t
ACL
, t
ACH
and t
SEXP
.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1516AS designs are supported by several third-party
tools. Automated fitters allow logic synthesis using a variety
of high-level description languages and formats.
Power-up Reset
The ATF1516AS is designed with a power-up reset, a fea-
ture critical for state machine initialization. At a point
delayed slightly from V
CC
crossing V
RST
, all registers will be
initialized, and the state of each output will depend on the
polarity of its buffer. However, due to the asynchronous
nature of reset and uncertainty of how V
CC
actually rises in
the system, the following conditions are required:
1. The V
CC
rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin
high, and,
3. The clock must remain stable during T
D
.
The ATF1516AS has two options for the hysteresis about
the reset level, V
RST
, Small and Large. During the fitting