Rainbow Electronics ADC12040 - Manual (Page 15)

Applications Information
(Continued)
TABLE 2. Input to Output Relationship —
Single-Ended Input
V
IN+
V
IN−
Output
V
CM
− V
REF
V
CM
0000 0000 0000
V
CM
− V
REF
/2 V
CM
0100 0000 0000
V
CM
V
CM
1000 0000 0000
V
CM
+ V
REF
/2 V
CM
1100 0000 0000
V
CM
+V
REF
V
CM
1111 1111 1111
1.3.1 Single-Ended Operation
single-ended performance is lower than with differential input
signals, so single-ended operation is not recommended.
However, if single-ended operation is required, one of the
analog inputs should be connected to the d.c. common
mode voltage of the driven input. The peak-to-peak differen-
tial input signal should be twice the reference voltage to
maximize SNR and SINAD performance (Figure 2b).
For example, set V
REF
to 1.0V and bias V
IN
− to 1.0V and
drive V
IN
+ with a signal range of 0V to 2.0V.
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
while maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC12040.
1.3.2 Driving the Analog Inputs
The V
IN
+ and the V
IN
− inputs of the ADC12040 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702 is a good amplifier for driving the ADC12040.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33
Ω series resistors at each of the signal
inputs with a 10 pF capacitor across the inputs, as can be
seen in Figure 5 and Figure 6. These components should be
placed close to the ADC because the input pins of the ADC
is the most sensitive part of the system and this is the last
opportunity to filter the input. The 10 pF capacitor is for
undersampling applications and should be replaced with a
68 pF capacitor for Nyquist applications.
Table 3 gives component values for Figure 5 to convert
signals to a range of 2.0V
± 1.0V at each of the differential
input pins of the ADC12040, assuming a V
REF
of 2.0V.
TABLE 3. Resistor Values for Circuit of Figure 5
SIGNAL
RANGE
R1 R2 R3 R4 R5, R6
0 - 0.5V 392 Ω 1540Ω 102Ω 115 Ω 1000Ω
0 - 1.0V 634 Ω 1470Ω 2490Ω 1050Ω 499Ω
± 0.25V 499 Ω 499 Ω 499 Ω 499 Ω 1000Ω
± 0.5V 100 Ω 200 Ω 100 Ω 200 Ω 499 Ω
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
CM
, should be in the
range of 0.4V to 4.0V and be of a value such that the peak
excursions of the analog input signal do not go more nega-
tive than ground or more positive than 1V below the V
A
supply voltage. The nominal V
CM
should generally be equal
to V
REF
/2, but V
RM
can be used as a V
CM
source as long as
V
RM
need not supply more than 10 µA of current.
2.0 DIGITAL INPUTS
Digital inputs consist of CLK, OE and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 50 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 kSPS.
The CLK pin should be terminated with a series 100 Ω resis-
tor and 51 pF capacitor to ground located within two centi-
meters of the ADC12040 clock pin, as shown in Figure 4.
Whenever the trace between the clock source and the ADC
clock pin is greater than 1 cm, use a 50
Ω series resistor in
the clock line, located within 1 cm of the driving source.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12040 will continue to convert whether
this pin is high or low, but the output can not be read while
the OE pin is high.
2.3 PD
The PD pin, when high, holds the ADC12040 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 70 mW
with a 40MHz clock and 40mW if the clock is stopped. The
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
3.0 OUTPUTS
The ADC12040 has 12 TTL/CMOS compatible Data Output
pins. Valid data is present at these outputs while the OE and
PD pins are low. While the t
OD
time provides information
about output timing, a simple way to capture a valid output is
to latch the data on the falling edge of the conversion clock
(pin 10). The output data format is offset binary.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
DR
and DR GND. These large charging current
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing and careful attention to the ground plane will
reduce this problem. Additionally, bus capacitance beyond
the specified 20 pF/pin will cause t
OD
to increase, making it
difficult to properly latch the ADC output data. The result
could be an apparent reduction in dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connect-
ADC12040
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