Rainbow Electronics ADC12040 - Manual (Page 17)

Applications Information
(Continued)
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12040
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 100 mV
P-P
.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be espe-
cially careful of this during turn on and turn off of power.
The V
DR
pin provides power for the output drivers and may
be operated from a supply in the range of 2.35V to V
D
(nominal 5V). This can simplify interfacing to 3V devices and
systems. DO NOT operate the V
DR
pin at a voltage higher
than V
D
.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are es-
sential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12040
between these areas, is required to achieve specified per-
formance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close prox-
imity to any of the ADC12040’s other ground pins.
Capacitive coupling between the typically noisy digital cir-
cuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients dur-
ing clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47
Ω to 100Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
20014815
FIGURE 6. Driving the Signal Inputs with a Transformer
ADC12040
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