10
AT25128A/256A [Preliminary]
3404A–SEEPR–10/03
Timing Diagrams (for SPI Mode 0 (0, 0))
Synchronous Data Timing
WREN Timing
WRDI Timing
SO
V
OH
OL
HI-Z
t
VALID IN
SI
IH
IL
H
SU
DIS
SCK
WH
CSH
CS
CSS
WL
HO