Ac timing characteristics – 5v operation at40k, At40k/at40klv series fpga – Rainbow Electronics AT40K40LV User Manual
Page 27
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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
CC
= 4.75V, temperature = 70
°C
Minimum times based on best case: V
CC
= 5.25V, temperature = 0
°C
Maximum delays are the average of t
PDLH
and t
PDHL
.
Clocks and Reset Input buffers are measured from a V
IH
of 1.5V at the input pad to the internal V
IH
of 50% of V
CC
.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
Cell Function
Parameter
Path
Device
-2
Units
Notes
Global Clocks and Set/Reset
GCLK Input Buffer
t
PD
(Maximum)
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
1.1
1.2
1.2
1.4
ns
ns
ns
ns
Rising edge clock
FCLK Input Buffer
t
PD
(Maximum)
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
0.7
0.8
0.8
0.8
ns
ns
ns
ns
Rising edge clock
Clock Column Driver
t
PD
(Maximum)
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
AT40K05
AT40K10
AT40K20
AT40K40
0.8
0.9
1.0
1.1
ns
ns
ns
ns
Rising edge clock
Clock Sector Driver
t
PD
(Maximum)
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
AT40K05
AT40K10
AT40K20
AT40K40
0.5
0.5
0.5
0.5
ns
ns
ns
ns
Rising edge clock
GSRN Input Buffer
t
PD
(Maximum)
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
AT40K05
AT40K10
AT40K20
AT40K40
3.0
3.7
4.3
5.6
ns
ns
ns
ns
From any pad to Global
Set/Reset network
Global Clock to Output
t
PD
(Maximum)
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
8.3
8.4
8.6
8.8
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Fast Clock to Output
t
PD
(Maximum)
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
7.9
8.0
8.1
8.3
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load