Rainbow Electronics AT25DF081 - Manual (Page 23)

23
3674E–DFLASH–8/08
AT25DF081
The complete one byte of data must be clocked into the device before the CS pin is deasserted,
and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); other-
wise, the device will abort the operation, the state of the SPRL bit will not change, no potential
Global Protect or Unprotect will be performed, and the WEL bit in the Status Register will be
reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Figure 10-2. Write Status Register
11. Other Commands and Functions
11.1 Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-
dor specific Extended Device Information.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh
must be clocked into the device. After the opcode has been clocked in, the device will begin out-
putting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00h
indicating that no Extended Device Information follows. After the Extended Device Information
String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional
clock cycles will have no affect on the SO pin and no data will be output. As indicated in the
JEDEC standard, reading the Extended Device Information String Length and any subsequent
data is optional.
Table 10-2. Write Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPRL X Global Protect/Unprotect X X
SCK
CS
SI
SO
MSB
2 3 1 0
0 0 0 0 0 0 0
6 7 5 4 10 11 9 8 14 15 13 12
OPCODE
MSB
1 D X D D D D X X
STATUS REGISTER IN
HIGH-IMPEDANCE