Rainbow Electronics DS1384 User Manual
Page 3
DS1384
3 of 17
V
CCO
- Switched DC power for SRAM (output): This pin will be connected to V
CC
when V
CC
voltage is
above V
SO
(the greater of V
BAT1
or V
BAT2
). When V
CC
voltage falls below this level, V
CCO
will be
connected to the higher voltage battery pin.
CEO
- RAM chip enable (output; active low): When power is good the
CE
input will be passed through
to
CEO
. If V
CC
is below V
PF
,
CEO
will remain at an inactive high level.
OER
- RAM output enable (output; active low): When power is good and the address value is not within
the range of 00000H and 0003FH, and
CE
is active, the
OE
input will be passed through to
OER
. If these
conditions are not met,
OER
will remain at an inactive high level.
CE
- Chip enable (input; active low): The chip enable signal must be asserted low during a bus cycle to
access the on-chip timekeeping RAM registers, or to access the external RAM via
CEO
.
OE
- Output enable (input; active low): The output enable signal identifies the time period when either
the RTC or the external SRAM drives the bus with read data, provided that
CE
is valid with
WE
disabled. When one of the 64 on-chip registers is selected during a read cycle, the
OE
is the enable signal
for the DS1384 output buffers and the data bus will be driven with read data. When the external RAM is
selected during a read cycle, the
OE
signal will be passed through to the
OER
pin so that read data will be
driven by the external SRAM.
WE
- Write enable (input; active low): The write enable signal identifies the time period during which
data is written to either the on-chip registers or to an external SRAM location. When one of the on-chip
64 registers is addressed, data will be written to the selected register on the rising edge of
WE
.
INTA
- Interrupt Output A (output; active low): Interrupt output A can be programmed as a Time of Day
Alarm or as a Watchdog Alarm (Interrupt output B becomes the alternate function). In addition,
INTA
can be programmed to output either a pulse or a level.
INTB
- Interrupt Output B (output; active high or low): Interrupt output B outputs the alarm (Time of
Day or Watchdog) that is not selected for
INTA
. Interrupt output B is programmable high or low.
Both
INTA
and
INTB
(INTB) are open drain outputs. The two interrupts and the internal clock continue to
run regardless of the level of V
CC
. However, it is important to insure that the pull-up resistors used with
the interrupt pins are never pulled up to a value which is greater than V
CC
+ 0.3V. As V
CC
falls below
approximately 3.0 volts, a power switching circuit turns the lithium energy source on the maintain the
clock, and timer data functionality. It is also required to insure that during this time (battery backup
mode), the voltage present at
INTA
and
INTB
(INTB) does never exceed V
BAT
. At all times the current on
each should not exceed +2.1 mA or -1.0 mA.
X1, X2 - Crystal inputs: Connections for a standard 32.768 kHz quartz crystal. When ordering, request a
load capacitance or 6 pF. The internal oscillator circuitry is designed for operation with a crystal having a
specified load capacitance (C
L
) of 6 pF.