Rainbow Electronics AT88SA100S - Manual (Page 4)

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AT88SA100S [Preliminary]
8558A–SMEM–03/09
1.4. Security Features
This chip incorporates a number of physical security features designed to protect the key from unauthorized release.
These include an active shield over the entire surface of the internal memory encryption, internal clock generation,
glitch protection, voltage tamper detection and other physical design features.
Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two
signals.
2. IO Protocol
Communications to and from this chip take place over a single asynchronously timed wire using a pulse count scheme.
The overall communications structure is a hierarchy:
Table 2. IO Hierarchy
Tokens Implement a single data bit transmitted on the bus, or the wake-up event.
Flags
Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any)
which may be transmitted.
Blocks
of data follow the command and transmit flags. They incorporate both a byte count and a checksum to
ensure proper data transmission
Packets
of bytes form the core of the block without the count and CRC. They are either the input or output
parameters of a AT88SA100S chip command or status information from the AT88SA100S chip
2.1. IO Tokens
There are a number of IO tokens that may be transmitted along the bus:
Input: (To device)
Wake Wake device up from sleep (low power) state
Zero Send a single bit from system to the device with a value of 0
One Send a single bit from system to the device with a value of 1
Output: (From the device)
ZeroOut Send a single bit from the device to the system with a value of 0
OneOut Send a single bit from the device to the system with a value of 1
The waveforms are the same in either direction, however there are some differences in timing based on the expectation
that the host has a very accurate and consistent clock while the device has significant variation in its internal clock
generator due to normal manufacturing and environmental fluctuations.
The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens
efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by the
device. Refer to Applications Notes on Atmel’s website for more details describing how the UART should be controlled.