Rainbow Electronics DS1855 - Manual (Page 15)

DS1855
15 of 20
NOTES:
1. All voltages are referenced to ground.
2. I
STBY
specified with for V
CC
= 3.0V and 5.0V, and control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
CC
for
the corresponding inactive state.
3. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
4. A fast mode-device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
5. After this period, the first clock pulse is generated.
6. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
7. C
B
– Total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
CC
) and (0.1)(V
CC
).
8. EEPROM write begins after a STOP condition occurs.
9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
positions.
11. I
CC
specified with SDA pin open.
12. Maximum I
CC
is dependent on clock rates.