5 read otp security register, Sck cs si so – Rainbow Electronics AT25DL081 User Manual
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AT25DL081 [DATASHEET]
8732D–DFLASH–12/2012
10.5 Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum
clock frequency specified by f
MAX
. To read the OTP Security Register, the CS pin must first be asserted and then the
opcode 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP
Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been
read, the device will continue reading from the beginning of the register (000000h). No delays will be incurred when
wrapping around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 10-5. Read OTP Security Register
SCK
CS
SI
SO
MSB
MSB
2
3
1
0
0
1
1
1
0
1
1
1
6
7
5
4
10 11
9
8
12
33
36
35
34
31 32
29 30
Opcode
A
A
A
A
A
A
A
A
A
X
X
X
MSB
MSB
D
D
D
D
D
D
D
D
D
D
Address Bits A23-A0
MSB
X
X
X
X
X
X
Don't Care
Data Byte 1
High-impedance