Rainbow Electronics AT25DL081 - Manual (Page 7)

7 AT25DL081 [DATASHEET]
8732D–DFLASH–12/2012
5. Device Operation
The AT25DL081 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25DL081 via the SPI bus, which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2, or 3), with each mode differing in respect to the
SCK polarity and phase, and how the polarity and phase control the flow of data on the SPI bus. The AT25DL081
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 5-1. SPI Mode 0 and 3
5.1 Dual-I/O Operation
The AT25DL081 features a Dual-Input Program mode and a Dual-Output Read mode that allow two bits of data to be
clocked into or out of the device every clock cycle to improve throughput. To accomplish this, both the SI and SO pins are
utilized as inputs/outputs for the transfer of data bytes. With the Dual-Input Byte/Page Program command, the SO pin
becomes an input along with the SI pin. Alternatively, with the Dual-Output Read Array command, the SI pin becomes an
output along with the SO pin. For both Dual-I/O commands, the SO pin will be referred to as the SOI
(Serial Output/Input) pin and the SI pin will be referred to as the SIO (Serial Input/Output) pin.
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction-dependent
information, such as address and data bytes, would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DL081 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DL081 memory array is FFFFFh, address bits A23-A20 are always ignored by
the device.
SCK
CS
SI
SO
MSB LSB
MSB LSB