Rainbow Electronics AT25040A - Manual (Page 8)

8
AT25010A/020A/040A [Preliminary]
3402A–SEEPR–10/3/03
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to
select one of four levels of protection. The AT25010A/020A/040A is divided into four
array segments. Top quarter (1/4), Top half (1/2), or all of the memory segments can be
protected. Any of the data within any selected segment will therefore be READ only. The
block write protection levels and corresponding status register control bits are shown in
Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g. WREN, t
WC
, RDSR).
READ SEQUENCE (READ): Reading the AT25010A/020A/040A via the SO (Serial
Output) pin requires the following sequence. After the CS line is pulled low to select a
device, the READ op-code (including A8) is transmitted via the SI line followed by the
byte address to be read (A7-A0). Upon completion, any data on the SI line will be
ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line.
If only one byte is to be read, the CS line should be driven high after the data comes out.
The READ sequence can be continued since the byte address is automatically incre-
mented and data will continue to be shifted out. When the highest address is reached,
the address counter will roll over to the lowest address allowing the entire memory to be
read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010A/020A/040A, the
Write Protect pin (WP) must be held high and two separate instructions must be exe-
cuted. First, the device must be write enabled via the Write Enable (WREN)
Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field loca-
tion selected by the Block Write Protection Level. During an internal write cycle, all
commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address (A7-A0) and the data (D7-D0) to be programm ed.
Programming will start after the CS pin is brought high. (The LOW to High transition of
the CS pin must occur during the SCK low time immediately after clocking in the D0
(LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STA-
TUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction
is enabled during the WRITE programming cycle.
Table 4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25010A AT25020A AT25040A
0 0 0 None None None
1 (1/4) 0 1 60-7F C0-FF 180-1FF
2 (1/2) 1 0 40-7F 80-FF 100-1FF
3 (All) 1 1 00-7F 00-FF 000-1FF