Rainbow Electronics AT89C5132 - Manual (Page 12)

12
AT8xC5132
4173A–8051–08/02
Clock Controller
The AT8xC5132 clock controller is based on an on-chip oscillator feeding an on-chip
Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are gener-
ated by this controller.
Oscillator The AT8xC5132 X1 and X2 pins are the input and the output of a single-stage on-chip
inverter (see Figure 5) that can be configured with off-chip components such as a Pierce
oscillator (see Figure 6). Value of capacitors and crystal characteristics are detailed in
the Section “DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU
core, and a clock for the peripherals as shown in Figure 5. These clocks are either
enabled or disabled, depending on the power reduction mode as detailed in “Power
Management” on page 46. The peripheral clock is used to generate the Timer 0, Timer
1, MMC, ADC, SPI, and Port sampling clocks.
Figure 5. Oscillator Block Diagram and Symbol
Figure 6. Crystal Connection
X2 Feature Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,
the AT8xC5132 need only 6 oscillator clock periods per machine cycle. This feature
called the “X2 feature” can be enabled using the X2 bit
(1) in CKCON (see Table 16) and
allows the AT8xC5132 to operate in 6 or 12 oscillator clock periods per machine cycle.
As shown in Figure 5, both CPU and peripheral clocks are affected by this feature.
Figure 7 shows the X2 mode switching waveforms. After reset, the standard mode is
activated. In standard mode, the CPU and peripheral clock frequency is the oscillator
frequency divided by 2 while in X2 mode, it is the oscillator frequency.
Note: 1. The X2 bit reset value depends on the X2B bit in the Hardware Byte (see Table 21 on
page 23). Using the AT89C5132 (Flash Version) the system can boot either in stan-
dard or X2 mode depending on the X2B value. Using AT83C5132 (ROM Version) the
system always boots in standard mode. X2B bit can be changed to X2 mode later by
software.
X1
X2
PD
PCON.1
IDL
PCON.0
Peripheral
CPU Core
0
1
X2
CKCON.0
÷
2
PER
CLOCK
Clock
Clock
Peripheral Clock Symbol
CPU
CLOCK
CPU Core Clock Symbol
OSC
CLOCK
Oscillator Clock Symbol
Oscillator
Clock
V
SS
X1
X2
Q
C1
C2