Rainbow Electronics AT89C5132 - Manual (Page 121)

121
AT8xC5132
4173A–8051–08/02
Figure 96. SPI Slave Mode Block Diagram
Note: MSTR bit in SPCON is cleared to select slave mode.
Bit Rate The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and
SPR0 control Bits in SPCON according to Table 113. These bit rates are derived from
the peripheral clock (F
PER
) issued from the Clock Controller block as detailed in
Section “Clock Controller”, page 12.
Table 113. Serial Bit Rates
Notes: 1. These frequencies are achieved in X1 mode, F
PER
= F
OSC
÷ 2.
2. These frequencies are achieved in X2 mode, F
PER
= F
OSC
.
Data Transfer The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle
state
(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the
input data are sampled and the edges on which the output data are shifted (see
Figure 97 and Figure 98). The SI signal is output from the selected slave and the SO
signal is the output from the master. The AT8xC5132 captures data from the SI line
while the selected slave captures data from the SO line.
For simplicity, the following figures depict the SPI waveforms in idealized form and do
not provide precise timing information. For timing parameters refer to the Section “AC
Characteristics”.
Note: 1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
MISO/P4.2
MOSI/P4.1
SS/P4.3 SPIF
SPSTA.7
CPOL
SPCON.3
CPHA
SPCON.2
8-bit Shift Register
SPDAT WR
I Q
In
te
rnal Bus
SPDAT RD
SCK/P4.2
SSDIS
SPCON.5
Control and Clock Logic
SPR2 SPR1 SPR0
Bit Rate (kHz) Vs F
PER
F
PER
Divider 6 MHz (1) 8 MHz (1)
10 MHz (1) 12 MHz (2) 16 MHz (2) 20 MHz (2)
0 0 0 3000 4000 5000 6000 8000 10000 2
0 0 1 1500 2000 2500 3000 4000 5000 4
0 1 0 750 1000 1250 1500 2000 2500 8
0 1 1 375 500 625 750 1000 1250 16
1 0 0 187.5 250 312.5 375 500 625 32
1 0 1 93.75 125 156.25 187.5 250 312.5 64
1 1 0 46.875 62.5 78.125 93.75 125 156.25 128
1 1 1 6000 8000 10000 12000 16000 20000 1