4 spi slave port, Spi slave port, Figure 5: spi slave port timing – Rainbow Electronics 78M6631 User Manual
Page 22: Table 17: spi slave port timing
Advertising
78M6631 Data Sheet
DS_6631_056
22
Rev 1
2.5.4 SPI Slave Port
Table 17: SPI Slave Port Timing
Parameter
Condition
Min
Typ
Max
Unit
t
SPIcyc
PCLK cycle time
1
µ
s
t
SPILead
Enable lead time
15
ns
t
SPILag
Enable lag time
0
ns
t
SPIW
PCLK pulse width
High
40
ns
Low
40
t
SPISCK
PCSZ to first PCLK fall
Ignore if PCLK is low
when PCSZ falls
2
ns
t
SPIDIS
Disable time
0
ns
t
SPIEV
PCLK to Data Out
15
ns
t
SPISU
Data input setup time
10
ns
t
SPIH
Data input hold time
5
ns
MSB OUT
LSB OUT
MSB IN
LSB IN
t
SPIcyc
t
SPILead
t
SPILag
t
SPISCK
t
SPIH
t
SPIW
t
SPIEV
t
SPIW
t
SPIDIS
PCSZ
PCLK
PSDI
PSDO
Figure 5: SPI Slave Port Timing
Advertising