Rainbow Electronics ATA6624 - Manual (Page 15)

15
4986F–AUTO–07/08
ATA6622/ATA6624/ATA6626
6. Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)
input within a time window of T
w d
. The trigger signal must exceed a minimum time
t
trigmin
> 200 ns. If a triggering signal is not received, a reset signal will be generated at output
NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period,
T
osc
, is adjustable via the external resistor R
wd_osc
(34 k
Ω
to 120 k
Ω
).
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES
disappears. It is defined as lead time t
d
. After wake up from Sleep or Silent Mode, the lead time
t
d
starts with the negative edge of the RXD output.
6.1 Typical Timing Sequence with R
WD_OSC
= 51 k
Ω
The trigger signal T
wd
is adjustable between 20 ms and 64 ms using the external resistor
R
WD_OSC
.
For example, with an external resistor of R
WD_OSC
= 51 k
Ω
±1%, the typical parameters of the
watchdog are as follows:
t
osc
= 0.405
×
R
WD_OSC
– 0.0004
×
(R
WD_OSC
) 2 (R
WD_OSC
in k
Ω
; t
osc
in µs)
t
OSC
= 19.6 µs due to 51 k
Ω
t
d
= 7895
×
19.6 µs = 155 ms
t
1
= 1053
×
19.6 µs = 20.6 ms
t
2
= 1105
×
19.6 µs = 21.6 ms
t
nres
= constant = 4 ms
After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output
NRES stays low for the time t
reset
(typically 4 ms), then it switches to high, and the watchdog
waits for the trigger sequence from the microcontroller. The lead time, t
d
, follows the reset and is
t
d
= 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-
ger pulse NTRIG occurs during this time, the time t
1
starts immediately. If no trigger signal
occurs during the time t
d
, a watchdog reset with t
NRES
= 4 ms will reset the microcontroller after
t
d
= 155 ms. The times t
1
and t
2
have a fixed relationship between each other. A triggering signal
from the microcontroller is anticipated within the time frame of t
2
= 21.6 ms. To avoid false trig-
gering from glitches, the trigger pulse must be longer than t
TRIG,min
> 200 ns. This slope serves to
restart the watchdog sequence. If the triggering signal fails in this open window t
2
, the NRES
output will be drawn to ground. A triggering signal during the closed window t
1
immediately
switches NRES to low.