Rainbow Electronics ATA6832 - Manual (Page 7)

7
4951A–AUTO–08/06
ATA6832
3.4 Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, T
jPW set
, the temperature prewarning bit (TP) in the output register is set. When the
temperature falls below the thermal prewarning threshold, T
jPW reset
, the bit TP is reset. The TP
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of an output stage exceeds the thermal shutdown threshold, T
jswitch off
,
the affected output is disabled and the corresponding bit in the output register is set to low. Addi-
tionally, the overload detection bit (OVL) in the output register is set. The output can be enabled
again when the temperature falls below the thermal shutdown threshold, T
jswitch on
, and the SRR
bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown thresh-
old avoids oscillations.
3.5 Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an
output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, fol-
lowing a delay time (t
dSd
). The over-load detection bit (OVL) is set and the corresponding status
bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and
the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the
OVL bit is reset and the disabled outputs are enabled.
3.6 Inhibit
The SI bit in the input register has to be set to zero to inhibit the ATA6832.
In this state, all output stages are then turned off but the serial interface remains active. The out-
put stages can be reactivated by setting bit SI to “1”.
3.7 PWM Mode
The common input for all six outputs is pin PWM ( Figure 3-2 ). The selection of the outputs,
which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM
input register, the corresponding input registers HSx and LSs have to be set.
Switching the high side outputs is possible up to 25 kHz, low side switches up to 8 kHz.
Figure 3-2. Output Control by PWM
Pin OUTx
Bit LSx/HSx
Bit PLx/PHx
Pin PWM