Rainbow Electronics ADC12D040 - Manual (Page 17)

Applications Information
(Continued)
TABLE 1. Input to Output Relationship —
Differential Input
V
IN+
V
IN−
Binary Output
2’s Complement
Output
V
CM
−
V
REF
/2
V
CM
+
V
REF
/2
0000 0000 0000 1000 0000 0000
V
CM
−
V
REF/4
V
CM
+
V
REF
/4
0100 0000 0000 1100 0000 0000
V
CM
V
CM
1000 0000 0000 0000 0000 0000
V
CM
+
V
REF
/4
V
CM
−
V
REF
/4
1100 0000 0000 0100 0000 0000
V
CM
+
V
REF
/2
V
CM
−
V
REF
/2
1111 1111 1111 0111 1111 1111
TABLE 2. Input to Output Relationship —
Single-Ended Input
V
IN+
V
IN
− Binary Output
2’s Complement
Output
V
CM
−
V
REF
V
CM
0000 0000 0000 1000 0000 0000
V
CM
−
V
REF
/2
V
CM
0100 0000 0000 1100 0000 0000
V
CM
V
CM
1000 0000 0000 0000 0000 0000
V
CM
+
V
REF
/2
V
CM
1100 0000 0000 0100 0000 0000
V
CM
+
V
REF
V
CM
1111 1111 1111 0111 1111 1111
1.3.1 Single-Ended Operation
Single-ended performance is lower than with differential in-
put signals. For this reason, single-ended operation is not
recommended. However, if single ended-operation is re-
quired and the resulting performance degradation is accept-
able, one of the analog inputs should be connected to the
d.c. mid point voltage of the driven input. The peak-to-peak
differential input signal should be twice the reference voltage
to maximize SNR and SINAD performance (Figure 2b).
For example, set V
REF
to 1.0V, bias V
IN
− to 2.5V and drive
V
IN
+ with a signal range of 1.5V to 3.5V.
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
when maintaining a full-range output. Table 1. Input to Out-
put Relationship —
Differential
Input and Table 2. Input to Output
Relationship —
Single-Ended Input indicate the input to output relationship
of the ADC12D040.
1.3.2 Driving the Analog Input
The V
IN
+ and the V
IN
− inputs of the ADC12D040 consist of
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog inputs. The best amplifiers
for driving the ADC12D040 input pins must be able to react
to these spikes and settle before the switch opens and
another sample is taken. The LMH6702 LMH6628 and the
LMH6622, LMH6655 are good amplifiers for driving the
ADC12D040.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 4
and Figure 5. These components should be placed close to
the ADC inputs because the input pins of the ADC is the
most sensitive part of the system and this is the last oppor-
tunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. Setting the
pole in this manner will provide best SNR performance.
To obtain best SINAD and ENOB performance, reduce the
RC time constant until SNR and THD are numerically equal
to each other. To obtain best distortion and SFDR perfor-
mance, eliminate the RC altogether.
For undersampling applications, the RC pole should be set
at about 1.15 times the maximum input frequency for narrow
band applications. For wide band applications, the RC pole
should be set at about 1.5 times the maximum input fre-
quency to maintain a linear delay response.
A single-ended to differential conversion circuit is shown in
Figure 5 and Table 3. Resistor Values for Circuit of NS4771
gives resistor values for that circuit to provide input signals in
a range of 2.5V
± 2.0V at each of the differential input pins of
the ADC12D040.
20046012
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
ADC12D040
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