Rainbow Electronics AT17F080 - Manual (Page 6)

6
AT17F040/080
3039C–CNFG–11/02
RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver.
CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the 2-wire Serial Programming
mode (SER_EN Low).
GND Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
CEO Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. If the PAGE_EN input is set High, the maximum value is
the highest address in the selected partition. The PAGESEL[1:0] inputs are used to
make the 4 partition selections. If the PAGE_EN input is set Low, the device is not parti-
tioned and the address maxvalue is the highest address in the device, see Table 2 on
page 5. In a daisy chain of AT17F Series devices, the CEO pin of one device must be
connected to the CE input of the next device in the chain. It will stay Low as long as CE
is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again.
A2 Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (recommended 4.7 k
W pull-up on this pin if used).
SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN
should be tied to V
CC
.
V
CC
+3.3V (±10%).