Rainbow Electronics DS1993 - Manual (Page 14)

DS1992/DS1993/DS1994
14 of 23 102199
WRITE PROTECT/PROGRAMMABLE EXPIRATION (DS1994)
The write protect bits (WPR, WPI, WPC) provide a means of write protecting the timekeeping data and
limiting access to the DS1994 when an alarm occurs (programmable expiration). The write protect bits
may not be written by performing a single copy scratchpad command. Instead, to write these bits, the
copy scratchpad command must be performed three times. Please note that the AA bit will set, as
expected, after the first copy command is successfully executed. Therefore, the authorization pattern for
the second and third copy command should have this bit set. The read scratchpad command may be used
to verify the authorization pattern.
The write protect bits, once set, permanently write protect their corresponding counter and alarm
registers, all write protect bits, and certain control register bits as shown in Figure 7. The time/count
registers will continue to count if the oscillator is enabled. If the user wishes to set more than one write
protect bit, the user must set them at the same time. Once a write protect bit is set it cannot be undone,
and the remaining write protect bits, if not set, cannot be set. The programmable expiration takes place
when one or more write protect bits have been set and a corresponding alarm occurs. If the RO (read
only) bit is set, only the read scratch and read memory function commands are available. If the RO bit is a
logic “0”, no memory function commands are available. The ROM functions are always available.
WRITE PROTECT CHART Figure 7
WRITE PROTECT BIT SET: WPR WPI WPC
Data Protected from
User Modification: Real Time Clock
Real Time Alarm
WPR
WPI
WPC
RO
OSC* Interval Timer
Interval Time Alarm
WPR
WPI
WPC
RO
OSC*
STOP/START **
AUTO/MAN Cycle Counter
Cycle Counter Alarm
WPR
WPI
WPC
RO
OSC*
DSEL
* Becomes write “1” only, i.e., once written to a logic “1”, may not be written back to a logic “0”.
** Forced to a logic “0”.
1-WIRE BUS SYSTEM
The 1-wire bus is a system which has a single bus master and one or more slaves. In most instances the
DS199X behaves as a slave. The exception is when the DS1994 generates an interrupt due to a
timekeeping alarm. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-wire bus must have open
drain or 3–state outputs. The 1-wire port of the DS199X is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1–Wire bus with multiple slaves attached. The 1-
wire bus has a maximum data rate of 16.3k bits per second and requires a pull-up resistor of
approximately 5 k
Ω
. The idle state for the 1-wire bus is high. If for any reason a transaction needs to be
suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and
the bus is left low for more than 120
µ
s, one or more of the devices on the bus may be reset.