Rainbow Electronics DS1993 - Manual (Page 17)

DS1992/DS1993/DS1994
17 of 23 102199
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1–
Wire bus or their 64–bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64–bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3–step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3–step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
Search Interrupt [ECh] (DS1994)
This ROM command works exactly as the normal ROM Search, but it will identify only devices with
interrupts that have not yet been acknowledged.
1–WIRE SIGNALING
The DS199x requires strict protocols to ensure data integrity. The protocol consists of five types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data
and interrupt pulse (DS1994). All these signals except presence pulse and interrupt pulse are initiated by
the bus master. The initialization sequence required to begin any communication with the DS199x is
shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS199x is ready to send or
receive data given the correct ROM command and memory function command. The bus master transmits
(TX) a reset pulse (t
RSTL
, minimum 480
µ
s). The bus master then releases the line and goes into receive
mode (RX). The 1–Wire bus is pulled to a high state via the pull–up resistor. After detecting the rising
edge on the data line, the DS199x waits (t
PDH
, 15–60
µ
s) and then transmits the presence pulse (t
PDL
, 60–
240
µ
s). There are special conditions if interrupts are enabled where the bus master must check the state
of the 1–Wire bus after being in the RX mode for 480
µ
s. These conditions will be discussed in the
“Interrupt” section.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS199x to the master
by triggering a delay circuit in the DS199x. During write time slots, the delay circuit determines when the
DS199x will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS199x will hold the data line low overriding the 1 generated by the master. If
the data bit is a “1”, the iButton will leave the read data time slot unchanged.