Rainbow Electronics AT45DB321B - Manual (Page 15)

15
AT45DB321B
2223D–DFLASH–10/02
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller.
3. For densities larger than 32M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
t
RST
t
REC
t
CSS
SI CMD 8 bits 8 bits 8 bits
MSB
Reserved for
larger densities
Page Address
(PA12-PA0)
Byte/Buffer Address
(BA9-BA0/BFA9-BFA0)
LSB r X X X X X X X X X X X X X X X X X X X X X X X