Rainbow Electronics MAX3799 - Manual (Page 28)

MAX3799
impromptu deemphasis adjustment, it is recommended
that the DE_INC (MODINC[5]) bit is used. Use of this bit
increments or decrements the deemphasis code setting
by 1 LSB based on the sign of increment in the
MODINC[4:0] and, hence, the SET_IMOD[8:0] setting.
This helps maintain the BER while having the flexibility to
improve signal quality by adjusting deemphasis while
the transmit operation continues. This feature enables
glitchless deemphasis adjustment while maintaining
excellent BER performance.
Activating Receiver Output Deemphasis
The RXDE_EN bit must be set to 1 to enable the deem-
phasis function. Deemphasis decreases the output
amplitude at ROUT+/ROUT- by 25%. To maintain the
same output amplitude as before the activation of
deemphasis, the SET_CML register value needs to be
increased by 25%. When deemphasis is enabled, the
limiting amplifier AC performance is guaranteed up to
800mV
P-P typical output amplitude. The SET_CML reg-
ister can be set from 0 to 255 bits, but it is important to
note that performance is guaranteed up to 215 bits.
Programming Pulse-Width Control
The eye crossing at the Tx output can be adjusted using
the SET_PWCTRL register. Table 6 shows these settings.
The sign of the number specifies the direction of pulse-
width distortion. The code of 1111 corresponds to a
balanced state for differential output. The pulse-width
distortion is bidirectional around the balanced state
(see the
Typical Operating Characteristics section).
Programming CML Output Settings
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude is up to 1000mV
P-P
with 4.6mV
P-P
resolution
(assuming an ideal 100 Ω differential load). The guaran-
teed output CML DAC range is up to 215.
Output Voltage R
OUT
(mV
P-P
) = 40 + 4.55 (SET_CML)
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors C IN and
C OUT should be selected to minimize the receiver’s
deterministic jitter. Jitter is decreased as the input low-
frequency cutoff (f
IN ) is decreased.
f IN = 1/[2 π(50)(C
IN )]
The recommended C IN and C OUT is 0.1μF for the
MAX3799.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC-offset cancellation
loop. To maintain stability, it is important to keep at
least a one-decade separation between f IN and the
low-frequency cutoff (f OC ) associated with the DC-off-
set cancellation circuit. A 1nF capacitor between CAZ1
and CAZ2 is recommended for the MAX3799.
Applications Information
Layout Considerations
To minimize inductance, keep the connections between
the MAX3799 output pins and laser diode as close as
possible. Optimize the laser diode performance by
placing a bypass capacitor as close as possible to the
laser anode. Use good high-frequency layout tech-
niques and multiple-layer boards with uninterrupted
ground planes to minimize EMI and crosstalk.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the MAX3799 and
must be soldered to the circuit board ground for proper
thermal and electrical performance. Refer to Application
Note 862:
HFAN-08.1: Thermal Considerations of QFN
and Other Exposed-Paddle Packages for additional
information.
Laser Safety and IEC 825
Using the MAX3799 laser driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections
must be considered. Each user must determine the
level of fault tolerance required by the application, rec-
ognizing that Maxim products are neither designed nor
authorized for use as components in systems intended
for surgical implant into the body, for applications
intended to support or sustain life, or for any other
application in which the failure of a Maxim product
could create a situation where personal injury or death
could occur.
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
28 ______________________________________________________________________________________
SET_PWCTRL[3:0] PWD SET_PWCTRL[3:0] PWD
1000 -7 0111 8
1001 -6 0110 7
1010 -5 0101 6
1011 -4 0100 5
1100 -3 0011 4
1101 -2 0010 3
1110 -1 0001 2
1111 0 0000 1
Table 6. Eye-Crossing Settings for
SET_PWCTRL