Asus Terminator A7VT400 - Manual (Page 79)

A S U S T e r m i n a t o r 1 A 7 V T 4 0 0 A S U S T e r m i n a t o r 1 A 7 V T 4 0 0 A S U S T e r m i n a t o r 1 A 7 V T 4 0 0 A S U S T e r m i n a t o r 1 A 7 V T 4 0 0 A S U S T e r m i n a t o r 1 A 7 V T 4 0 0 5 - 1 5 5 - 1 5 5 - 1 5 5 - 1 5 5 - 1 5
5.4.2 5.4.2 5.4.2 5.4.2 5.4.2 Memory configuration Memory configuration Memory configuration Memory configuration Memory configuration
The items in this menu show the memory configuration settings. Select an
item then press <Enter> to display a pop-up menu with the configuration
options.
DRAM Clock [By SPD] DRAM Clock [By SPD] DRAM Clock [By SPD] DRAM Clock [By SPD] DRAM Clock [By SPD]
Sets the DRAM frequency. Configuration options: [By SPD] [133 MHz]
[166 MHz]
DRAM Timing [Auto by SPD] DRAM Timing [Auto by SPD] DRAM Timing [Auto by SPD] DRAM Timing [Auto by SPD] DRAM Timing [Auto by SPD]
The DRAM clock is set according to DRAM SPD (Serial Presence Detect).
Select [Auto by SPD] for automatic DRAM clock detection. Select [Manual]
to set the DRAM Timing manually. Select [Safe] to set the DRAM timing to
safe value. Configuration options: [Auto by SPD] [Manual] [Safe]
DRAM Burst Length [4] DRAM Burst Length [4] DRAM Burst Length [4] DRAM Burst Length [4] DRAM Burst Length [4]
Sets the DRAM burst length width. Configuration options: [4] [8]
DRAM Command Rate [2T Command] DRAM Command Rate [2T Command] DRAM Command Rate [2T Command] DRAM Command Rate [2T Command] DRAM Command Rate [2T Command]
Sets the DRAM command rate .
Configuration options: [1T Command] [2T Command]
Write Recovery Time [3T] Write Recovery Time [3T] Write Recovery Time [3T] Write Recovery Time [3T] Write Recovery Time [3T]
Sets the DRAM write recovery time. Configuration options: [2T] [3T]
tWTR [2T] tWTR [2T] tWTR [2T] tWTR [2T] tWTR [2T]
Sets the tWTR time. Configuration options: [1T] [2T]
Memory Configuration Select Menu
Item Specific Help
Set DRAM Frequency.
Current DRAM Frequency 133 MHz
DRAM Clock [By SPD]
DRAM Timing [Auto by SPD]
x DRAM CAS Latency 2.5
x Bank Interleave Disabled
x Precharge to Active (Trp) 5T
x Active to Precharge (Tras) 7T
x Active to CMD (Trcd)
5T
DRAM Burst Length [4]
DRAM Command Rate [2T Command]
Write Recovery Time [3T]
tWTR [2T]