AAEON GENE-QM67 - Manual (Page 27)

S u b C o m p a c t B o a r d G E N E - Q M 6 7
Chapter 2 Quick Installation Guide 2 - 14
UNote:
LVDS2 VDD can be set to +5V or +12V by JP4. LVDS2 BKL_CTL can be set
by JP7.
2.25 Audio I/O Port (CN8)
Pin Signal
1 Microphone Left Channel
2 Microphone Left Channel
3 GND
4 Line-In Left Channel
5 Line-In Right Channel
6 GND
7 Line-Out Left Channel
8 GND
9 Line-Out Right Channel
10 +5V
2.26 LVDS Port 1 (CN9)
Pin Signal Pin Signal
1 BKL_EN 2 BKL_CTL
3 VCC 4 GND
5 CLK_A- 6 CLK_A+
7 VCC 8 GND
9 DATA_A0- 10 DATA_A0+
11 DATA_A1- 12 DATA_A1+
13 DATA_A2- 14 DATA_A2+
15 DATA_A3- 16 DATA_A3+
17 DDC_DAT 18 DDC_CLK
19 DATA_B0- 20 DATA_B0+
21 DATA_B1- 22 DATA_B1+