AAEON TKS-G50-QM77 - Manual (Page 113)

E m b e d d e d B o x T K S - G 5 0 - Q M 7 7
AppendixE Digital I/O Ports E - 4
E.3 Digital I/O Register
Table 2 : SuperIO relative register table
Default Value Note
Index 0x2E
SIO MB PnP Mode Index Register
0x2E or 0x4E
Data 0x2F
SIO MB PnP Mode Data Register
0x2F or 0x4F
Table 3 : Digital Input/Output relative register table
LDN Register BitNum Note
GPIO1 Direction 0x07 0xCE 0 0:input, 1: output
GPIO2 Direction 0x07 0xCE 1
GPIO3 Direction 0x07 0xCE 2
GPIO4 Direction 0x07 0xCE 3
GPIO5 Direction 0x07 0xCF 0
GPIO6 Direction 0x07 0xCF 1
GPIO7 Direction 0x07 0xCF 2
GPIO8 Direction 0x07 0xCF 3
Table 4: Digital Input/Output relative IO address table
IO Address BitNum Note
GPIO1 State 0x0A06 0 0:input, 1: output
GPIO2 State 0x0A06 1
GPIO3 State 0x0A06 2
GPIO4 State 0x0A06 3
GPIO5 State 0x0A07 0
GPIO6 State 0x0A07 1
GPIO7 State 0x0A07 2
GPIO8 State 0x0A07 3