AMD ATHLON 64 - Manual (Page 39)

Appendix A 39
Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™
ccNUMA Multiprocessor Systems
40555 Rev. 3.00 June 2006
Appendix A
The following sections provide additional explanatory information on topics discussed in the previous
sections of this document.
A.1 Description of the Buffer Queues
Figure 16 shows the internal resources in each Quartet node. The memory controller (MCT), the
System Request Interface (SRI) and the Crossbar (XBar) on each node all have internal buffers that
are used to queue transmitted transaction packets. Physically each of these units only has two kinds of
buffers, command and data.
Figure 16. Internal Resources Associated with a Quartet Node
Consider the buffers that come into play in the interface between the XBar and the HyperTransport™
links.
Each node has an incoming and outgoing coherent HyperTransport link on its XBar to every other
node but one in the system. Node 0 has an outgoing link that allows it to send data from node 0 to
node 1. Likewise node 0 has an incoming link from node 1 to node 0. The two links together can be
considered as one bidirectional link.
Each node has HyperTransport buffers in its XBar that are used to queue up the packets that are going
to be sent on the outgoing link. The sending node does not send the packets until the receiving node is
ready to receive them.
Now Consider the buffers that come into play in the interface between the XBar and the MCT.
Packets to be transmitted from the XBar to the MCT are queued in the ‘XBar-to-MCT” buffers.
HT = HyperTransport™
cHT = coherent HyperTransport
C0
C1