10 video input port register descriptions, Video input port register descriptions, Table 6-75 – AMD Geode LX [email protected] User Manual

Page 482: Standard geodelink™ device msrs summary, Table 6-76, Vip configuration/control registers summary

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482

AMD Geode™ LX Processors Data Book

Video Input Port Register Descriptions

33234H

6.10

Video Input Port Register Descriptions

The registers associated with the VIP are the Standard
GeodeLink Device (GLD) MSRs (accessed via the RDMSR
and WRMSR instructions) and VIP Configuration/Control
Registers. Table 6-75 and Table 6-76 are register summary

tables that include reset values and page references where
the bit descriptions are provided.

Note:

The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 f
or more details on MSR addressing.

Table 6-75. Standard GeodeLink™ Device MSRs Summary

MSR Address

Type

Register Name

Reset Value

Reference

54002000h

RO

GLD Capabilities MSR (GLD_MSR_CAP)

00000000_ 0003C4xxh

Page 484

54002001h

R/W

GLD Configuration MSR
(GLD_MSR_CONFIG)

000000000_ 00000000h

Page 484

54002002h

R/W

GLD SMI MSR (GLD_MSR_SMI)

000000000_ xxxx7FFFh

Page 485

54002003h

R/W

GLD Error MSR (GLD_MSR_ERROR)

000000000_ 00000000h

Page 486

54002004h

R/W

GLD Power Management Register
(GLD_MSR_PM)

000000000_ 00000005h

Page 487

54002005h

R/W

GLD Diagnostic MSR (GLD_MSR_DIAG)

000000000_ 00000000h

Page 487

Table 6-76. VIP Configuration/Control Registers Summary

VIP Memory

Offset

Type

Register Name

Reset Value

Reference

00h

R/W

VIP Control Register 1 (VIP_CTL_REG1)

42000001h

Page 488

04h

R/W

VIP Control Register 2 (VIP_CTL_REG2)

00000000h

Page 490

08h

R/W

VIP Status (VIP_STATUS)

xxxxxxxxh

Page 492

0Ch

R/W

VIP Interrupt (VIP_INT)

xxxxFFFEh

Page 494

10h

R/W

VIP Current/Target (VIP_CUR_TAR)

00000000h

Page 495

14h

R/W

VIP Max Address (VIP_MAX_ADDR)

FFFFFFFFh

Page 495

18h

R/W

VIP Task A Video Even Base Address
(VIP_TASK_A_VID_EVEN_BASE)

00000000h

Page 496

1Ch

R/W

VIP Task A Video Odd Base Address
(VIP_TASK_A_VID_ODD_BASE)

00000000h

Page 496

20h

R/W

VIP Task A VBI Even Base Address
(VIP_TASK_A_VBI_EVEN_BASE)

00000000h

Page 497

24h

R/W

VIP Task A VBI Odd Base Address
(VIP_TASK_A_VBI_ODD_BASE)

00000000h

Page 497

28h

R/W

VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)

00000000h

Page 498

2Ch

R/W

VIP Control Register 3 (VIP_CONTRL_REG3)

00000020h

Page 498

30h

R/W

VIP Task A V Offset (VIP_TASK_A_V_OFFSET)

00000000h

Page 499

34h

R/W

VIP Task A U Offset (VIP_TASK_A_U_OFFSET)

00000000h

Page 500

38h

R/W

VIP Task B Video Even Base/Horizontal End
(VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)

00000000h

Page 500

3Ch

R/W

VIP Task B Video Odd Base/Horizontal Start
(VIP_TASK_B_VID_ODD_BASE_HORIZ_START)

00000000h

Page 501

40h

R/W

VIP Task B VBI Even Base/VBI End
(VIP_TASK_B_VBI_EVEN_BASE_VBI_END)

00000000h

Page 501

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