AMD Athlon 6 - Manual (Page 9)

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24332G—October 2003 AMD Athlon™ Processor Model 6 Revision Guide
Preliminary Information
18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle
Products Affected. A0, A2
Normal Specified Operation. The first processor cycle after a FID Change special cycle should be a Connect
special cycle.
Non-conformance. In rare circumstances, a processor victim write may be pending inside the processor
when the FID Change special cycle is issued. Several bus clocks later, the WrVictimBlk command for
the victim will be issued. This violates the specification, which states that all processor-based
commands should be finished before the FID change special cycle.
Potential Effect on System. The core logic may become confused.
Suggested Workaround. System core logic can wait for numerous bus clocks after receiving the FID change
special cycle before attempting to disconnect in order to generate a window sufficiently large enough
to allow the WrVictimBlk transaction to take place prior to the disconnect.
Resolution Status. Fix planned for a future revision.