IEI Integration ICE-DB-T6 - Manual (Page 31)

Type 6 Carrier Board Design Guide
Page 21
D81
D82 PEG_TX9+
PEG_TX9- O PEG Port 9. Transmit Output differential pair.
C85
C86 PEG_RX10+
PEG_RX10- I PEG Port 10.. Receive Input differential pair.
D85
D86 PEG_TX10+
PEG_TX10- O PEG Port 10.Transmit Output differential pair.
C88
C89 PEG_RX11+
PEG_RX11- I PEG Port 11. Receive Input differential pair.
D88
D89 PEG_TX11+
PEG_TX11- O PEG Port 11. Transmit Output differential pair.
C91
C92 PEG_RX12+
PEG_RX12- I PEG Port 12. Receive Input differential pair.
D91
D92 PEG_TX12+
PEG_TX12- O PEG Port 12. Transmit Output differential pair.
C94
C95 PEG_RX13+
PEG_RX13- I PEG Port 13,. Receive Input differential pair.
D94
D95 PEG_TX13+
PEG_TX13- O PEG Port 13. Transmit Output differential pair.
C98
C99 PEG_RX14+
PEG_RX14- I PEG Port 14.. Receive Input differential pair.
D98
D99 PEG_TX14+
PEG_TX14- O PEG Port 14. Transmit Output differential pair.
C101
C102 PEG_RX15+
PEG_RX15- I PEG Port 15. Receive Input differential pair.
D101
D102 PEG_TX15+
PEG_TX15- O PEG Port 15. Transmit Output differential pair.
A88
A89 PCIE_CLK_REF
+
PCIE_CLK_REF- O PCIe Reference Clock for all COM Express
PCIe lanes, and for PEG lanes
D54 PEG_LANE_RV# I 3.3V
CMOS
PCI Express Graphics lane reversal input strap.
Pull low on the carrier board to reverse lane
order.
D97 PEG_ENABLE# I 3.3V
CMOS
PEG enable function. Strap to enable PCI
Express x16 external graphics interface. Pull low
to disable internal graphics and enable the x16
interface.
PS: IEI BIOS auto detects the SDVO or
PCIe x16, please reserve for future use
Table 3-1: PCI Express Signal Descriptions