Asus P4GD1 - Manual (Page 81)

A S U S P 4 G D 1 A S U S P 4 G D 1 A S U S P 4 G D 1 A S U S P 4 G D 1 A S U S P 4 G D 1 4 - 2 3 4 - 2 3 4 - 2 3 4 - 2 3 4 - 2 3
4.4.5 4.4.5 4.4.5 4.4.5 4.4.5 Chipset Chipset Chipset Chipset Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Select Screen
Select Item
CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto]
Disables or sets the CPU internal thermal control.
Configuration options: [Disabled] [Auto]
Hyper-Threading Technology [Enabled] Hyper-Threading Technology [Enabled] Hyper-Threading Technology [Enabled] Hyper-Threading Technology [Enabled] Hyper-Threading Technology [Enabled]
Allows you to enable or disable the processor Hyper-Threading Technology.
Configuration options: [Disabled] [Enabled]
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
Hyper-Path 2 [Auto]
Graphic Adapter Priority [PCI Express/PCI]
PEG Buffer Length [Auto]
Link Latency [Auto]
PEG Link Mode [Auto]
PEG Root Control [Auto]
Slot Power [Auto]
Advanced Chipset Settings Advanced Chipset Settings Advanced Chipset Settings Advanced Chipset Settings Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled] Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [3 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [3 Clocks] [2.5 Clocks] [2 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks] [3 Clocks]
[4 Clocks] [5 Clocks]