Av8 dolby digital and thx dsp, L896ct – Arcam Preamp Processor AV8 User Manual
Page 58
ISSUE
DRAWING NO.
DRAWING TITLE
DATE
Filename:
ECO No.
DESCRIPTION OF CHANGE
AVD DD DSP.sch
AV8 Dolby Digital and THX DSP
Contact Engineer:
L896CT
1-Aug-2002
INITIALS
Printed:
7
11
Sheet
of
Notes:
Contact Tel:
(01223) 203200
EngName A Dutton
A & R Cambridge Ltd.
Pembroke Avenue
Cambridge CB5 9PB
Waterbeach
23425
VD1
1
DGND1
2
AUDDATA3/XMT958
3
WR,DS,EMWR,GPIO10
4
RD,R/W,EMOE,GPIO11
5
A1,SCDIN
6
A0,SCCLK
7
DATA7,EMAD7,GPIO7
8
DATA6,EMAD6,GPIO6
9
DATA5,EMAD5,GPIO5
10
DATA4,EMAD4,GPIO4
11
VD2
12
DGND2
13
DATA3,EMAD3,GPIO3
14
DATA2,EMAD2,GPIO2
15
DATA1,EMAD1,GPIO1
16
DATA0,EMAD0,GPIO0
17
CS
18
SCDIO,SCDOUT,PSEL,GPIO9
19
BOOT,INTREQ
20
EXTMEM,GPIO8
21
SDATAN1
22
VD3
23
DGND3
24
SCLKN1,STCCLK2
25
LRCLKN1
26
CPMDAT,SDATAN2,RCV958
27
CMPCLK,SCLKN2
28
CMPREQ,LRCLKN2
29
CLKIN
30
CLKSEL
31
FILT2
32
FILT1
33
VA
34
AGND
35
RESET
36
DD (RESERVED)
37
DC (RESERVED)
38
AUDATA2
39
AUDATA1
40
AUDATA0
41
LRCLK
42
SCLK
43
MCLK
44
CS49326
IC701
CS49326
P2V5D
DGND
70R@100MHz
L700
7F004
DGND
P2V5A1
C712
100N 0805
C710
100N 0805
C708
100N 0805
C716
100N 0805
+ C711
1U0 EL
+ C709
1U0 EL
+ C717
1U0 EL
+ C714
47U EL 35V
P2V5D
DGND
P2V5A2
+
C702
2U2 EL
P2V5A1
DGND
SPDIF I2S BCLK
SPDIF I2S LRCLK
SPDIF I2S DATA
ADC I2S SCLK
ADC I2S LRCLK
SPDIF ADC TX
R717
4K7 0805
R718
4K7 0805
P2V5D
P2V5D
DSP1_MCLK
R700
10K 0805 1%
P2V5D
DGND
DGND
P2V5A2
+
C705
2U2 EL
P2V5A2
DGND
R724
4K7 0805
R725
4K7 0805
P2V5D
P2V5D
DSP2_MCLK
70R@100MHz
L701
7F004
C721
100N 0805
C720
100N 0805
C719
100N 0805
C726
100N 0805
+ C725
1U0 EL
+ C735
1U0 EL
+ C724
1U0 EL
+ C727
1U0 EL
+ C736
47U EL 35V
P2V5D
DGND
P2V5A1
DSP_D0
DSP_D1
DSP_D2
DSP_D3
DSP_D4
DSP_D5
DSP_D6
DSP_D7
SCDIN
SCCLK
DSP1 CS
DSP1_INTREQ
SCDIN
SCCLK
DSP2 CS
WR
ADC DATA
1
2
3
4
5
6
7
8
RP702
100R X 4 ISO
R712
100R 0805
R715
100R 0805
DSP1_SCLK
DSP1_LRCLK
DSP1_AUD0
DSP1_AUD0
DSP1_SCLK
DSP1_LRCLK
CPU24.576MHz
CPU24.576MHz
SCDIN
SCCLK
DSP1 CS
DSP1_INTREQ
DSP_RESET1
SCDIN
SCCLK
DSP1 CS
DSP1_INTREQ
DSP_RESET1
DSP2 CS
DSP2_INTREQ
DSP2 CS
DSP2_INTREQ
CPU24.576MHz
DSP2_MCLK
DSP1_MCLK
DSP_RESET1
DSP2_INTREQ
SPDIF I2S DATA
SPDIF I2S BCLK
SPDIF I2S LRCLK
SPDIF ADC TX
R736
100R 0805
R738
100R 0805
R737
100R 0805
R726
10K 0805 1%
R719
10K 0805 1%
C707
10N 0805
C704
10N 0805
VD1
1
DGND1
2
AUDDATA3/XMT958
3
WR,DS,EMWR,GPIO10
4
RD,R/W,EMOE,GPIO11
5
A1,SCDIN
6
A0,SCCLK
7
DATA7,EMAD7,GPIO7
8
DATA6,EMAD6,GPIO6
9
DATA5,EMAD5,GPIO5
10
DATA4,EMAD4,GPIO4
11
VD2
12
DGND2
13
DATA3,EMAD3,GPIO3
14
DATA2,EMAD2,GPIO2
15
DATA1,EMAD1,GPIO1
16
DATA0,EMAD0,GPIO0
17
CS
18
SCDIO,SCDOUT,PSEL,GPIO9
19
BOOT,INTREQ
20
EXTMEM,GPIO8
21
SDATAN1
22
VD3
23
DGND3
24
SCLKN1,STCCLK2
25
LRCLKN1
26
CPMDAT,SDATAN2,RCV958
27
CMPCLK,SCLKN2
28
CMPREQ,LRCLKN2
29
CLKIN
30
CLKSEL
31
FILT2
32
FILT1
33
VA
34
AGND
35
RESET
36
DD (RESERVED)
37
DC (RESERVED)
38
AUDATA2
39
AUDATA1
40
AUDATA0
41
LRCLK
42
SCLK
43
MCLK
44
CS49330
IC702
CS49330
DSP_RESET2
DSP_RESET2
DSP_RESET2
DGND
SCDOUT
SCDOUT
DGND
SCDOUT
SCDOUT
DIR
1
A0
2
B4
14
A1
3
B5
13
A2
4
B6
12
A3
5
B7
11
GND
10
A7
9
B3
15
A6
8
B2
16
A5
7
B1
17
A4
6
B0
18
OE
19
VCC
20
IC704
74LVC245A D
DGND
P3V3D
C728
100N 0805
DSP_D7
DSP_D6
DSP_D5
DSP_D4
DSP_D3
DSP_D2
DSP_D1
DSP_D0
D7
D6
D5
D4
D3
D2
D1
D0
OE
1
D0
2
Q5
14
D1
3
Q6
13
D2
4
Q7
12
D3
5
CP
11
GND
10
D7
9
Q4
15
D6
8
Q3
16
D5
7
Q2
17
D4
6
Q1
18
Q0
19
VCC
20
IC705
74LVC574A D
OE
1
D0
2
Q5
14
D1
3
Q6
13
D2
4
Q7
12
D3
5
CP
11
GND
10
D7
9
Q4
15
D6
8
Q3
16
D5
7
Q2
17
D4
6
Q1
18
Q0
19
VCC
20
IC706
74LVC574A D
OE
1
D0
2
Q5
14
D1
3
Q6
13
D2
4
Q7
12
D3
5
CP
11
GND
10
D7
9
Q4
15
D6
8
Q3
16
D5
7
Q2
17
D4
6
Q1
18
Q0
19
VCC
20
IC707
74LVC574A D
DSP_D0
DSP_D1
DSP_D2
DSP_D3
DSP_D4
DSP_D5
DSP_D6
DSP_D7
A7
A6
A5
A4
A3
A2
A1
A0
A7
A6
A5
A4
A3
A2
A1
A0
A15
A14
A13
A12
A11
A10
A9
A8
A10
A9
A8
A18
A17
A16
DGND
P3V3D
C734
100N 0805
DGND
P3V3D
C738
100N 0805
DGND
P3V3D
C740
100N 0805
DGND
DGND
DGND
EMOE
EMOE
EMOE
EMOE
DSP_D0
DSP_D1
DSP_D2
DSP_D3
DSP_D4
DSP_D5
DSP_D6
DSP_D7
P2V5D
A7
A6
A5
A4
A3
A2
A1
A0
A15
A14
A13
A12
A11
A10
A9
A8
A18
A17
A16
D0
D1
D2
D3
D4
D5
D6
D7
C742
100N 0805
70R@100MHz
L708
7F004
DGND
DGND
P3V3D
C743
100N 0805
C744
100N 0805
DGND
DGND
WR
RAMENABLE
RAMENABLE
RAMENABLE
SPDIF ADC TX
DGND
WR
EXTMEM
R707
10K 0805
EXTMEM
EXTMEM
A0
1
A1
2
A2
3
A3
4
A4
5
A5
14
A6
15
A7
16
A8
17
A9
18
A10
20
A11
21
A12
22
A13
23
A14
24
A15
32
A16
33
A17
34
A18
35
I/O 0
7
I/O 1
8
I/O 2
11
I/O 3
12
I/O 4
25
I/O 5
26
I/O 6
29
I/O 7
30
CE
6
OE
31
VCC
9
VCC
27
GND
10
GND
28
NC
19
WE
13
NC
36
CY7C1049BV33-15
512K x 8
STATIC RAM
IC708
CY7C1049BV33-15
1
2
3
4
5
6
7
8
CP703
100P X 4 ISO
DGND
1
2
3
4
5
6
7
8
CP700
100P X 4 ISO
DGND
+ C729
47U EL 35V
DGND
+ C718
47U EL 35V
DGND
DSP2 BCLK
DSP2 LRCLK
DATA LR
DATA CS
DATA LSRS
DATA LSBRSB
DGND
R720
180K 0805
R727
180K 0805
C706
220P NPO 0805
C703
220P NPO 0805
1
2
3
4
5
6
7
8
RP700
10K X 4 ISO
1
2
3
4
5
6
7
8
RP701
10K X 4 ISO
1
2
3
4
5
6
7
8
RP706
10K X 4 ISO
1
2
3
4
5
6
7
8
RP705
10K X 4 ISO
R701
3K3 0805 1%
R702
3K3 0805 1%
R702
3K3 0805 1%
R704
3K3 0805 1%
R708
3K3 0805 1%
R709
3K3 0805 1%
R710
3K3 0805 1%
R711
3K3 0805 1%
WAF
12/02/02
1.2
02_E044
R701 TO R704 & R708 TO R711 CHANGED TO 3K3 IC104 UPDATED
C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
02_101
WF/AD
16/5/02
IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE
1.3.0
02_E127
AD
27/06/02
Remove R803 for PLL board upgrade
1.4.0
02_E160
WAF
27/06/02
R921 FROM 10K TO 33K
1.5.0
02_E161
WAF
1/8/02
CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907
1.6.0