Apple Power Mac G5 - Manual (Page 10)

Frontside Bus up to 1GHz
To harness the power of the G5 processor, a 64-bit bidirectional Double Data Rate
(DDR) frontside bus maximizes throughput between the processor and the rest of
the system. Unlike conventional processor interfaces, which can carry data in only
one direction at a time, the PowerPC G5 features two dedicated, unidirectional 32-bit
data paths (64 bits total): one traveling into the processor and one traveling from the
processor. This enables data to move in opposite directions simultaneously—a dramatic
improvement over previous processor interfaces, because there is no delay while the
processor and the system controller negotiate which will use the bus or while the bus
switches direction. In addition, the data streams integrate clock signals along with the
data, allowing the frontside bus to work at speeds up to 1GHz for an industry-leading
8 GBps of bandwidth.
Dual processor systems get an even greater performance boost. Each G5 processor
has its own bidirectional interface to the system controller, for total bandwidth of up to
16 GBps, well over twice the 6.4-GBps maximum bandwidth of Pentium 4–based sys-
tems. In addition to providing fast throughput to main memory, this high-performance
frontside bus architecture enables each PowerPC G5 to discover and access data in the
other processor’s caches—further increasing bandwidth on dual processor systems.
Advanced System Controller
A new system controller is central to the overall performance of the Power Mac G5.
This revolutionary application-specific integrated circuit (ASIC)—one of the industry’s
fastest—is built using the same state-of-the-art IBM 130-nanometer process technology
as the PowerPC G5 processor. A superefficient point-to-point architecture provides each
primary subsystem with dedicated throughput to main memory, so massive amounts
of data can traverse the system without contention for bandwidth. In contrast, subsys-
tems that share a bus, as on other personal computers, must deal with time-consuming
arbitration while they negotiate for access and bandwidth across a common data path.
Memory up to 400MHz
The Power Mac G5 features a memory controller supporting 400MHz, 128-bit DDR
SDRAM.
2 DDR memory allows the system to read and write data on both the rising and
falling edge of each clock cycle. By combining fast DDR memory with a wider 128-bit
interface that can address two banks of SDRAM at a time, the Power Mac G5 can reach
a memory throughput of up to 6.4 GBps—more than double the throughput of the
Power Mac G4. For even greater performance, direct memory access (DMA) works with
the point-to-point system controller to give each subsystem—such as PCI and graphics
slots—its own 6.4-GBps interface to main memory, without needing to interact with
the processor.
With the 64-bit G5 processor, the Power Mac G5 can address more memory than any
previous Macintosh and many desktop PCs. The dual processor systems can hold up
to eight DIMMs for up to 8GB of memory. This high-speed, high-capacity memory
architecture enables graphics, video, audio, and scientific applications to run radically
faster. Enormous files and data sets can be loaded into RAM for rapid processing by
the PowerPC G5—without having to access system storage. Data is transferred to
memory 40 times faster than to the hard drive. In fact, accessing the first critical word
of data from memory is 60,000 times faster than from a hard drive, so manipulation
and analysis of data can be performed at remarkable speeds.
10 Technology and
Performance Overview
Power Mac G5
The bidirectional frontside bus allows data to
travel to and from the PowerPC G5 processor
at the same time. On dual processor systems,
each PowerPC G5 has its own dedicated inter-
face to maximize throughput—compared
with dual Xeon-based systems, which force
the processors to share a single bus.
PowerPC G5 PowerPC G5 Xeon Xeon