5 north bridge, 6 south bridge, Low mmio align [64m – Asus TS100-E7 User Manual

Page 73: Dmi gen2 [enabled, Vt-d [disabled, Initiate graphic adapter [peg/pci, High precision timer [enabled

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ASUS TS100-E7/PI4

4-17

4.5.5

North Bridge

The North Bridge is built in the CPU.

Aptio Setup Utility - Copyright (C) 2010 American Megatrends, Inc.

Advanced

Low MMIO resources align at

64MB/1024MB

Memory Information

TOTAL Memory

1024 MB

DIMM_A1

0 MB (DDR3 1333)

DIMM_A2

1024 MB (DDR3 1333)

DIMM_B1

0 MB (DDR3 1333)

DIMM_B2

0 MB (DDR3 1333)

Low MMIO Align

[64M]

DMI Gen2

[Enabled]

VT-d

[Disabled]

Initate Graphic Adapter [PEG/PCI]

Low MMIO Align [64M]

Allows you to select the options for the Low MMIO Align.

Configuration options: [64M] [1024M]

DMI Gen2 [Enabled]

Allows you to enable or disable the DMI Gen2.

Configuration options: [Disabled] [Enabled]

VT-d [Disabled]

Allows you to enable or disable the VT-d.

Configuration options: [Disabled] [Enabled]

Initiate Graphic Adapter [PEG/PCI]

Allows you to decide which graphics controller to use as the primary boot device.

Configuration options: [PCI/PEG] [PEG/PCI]

4.5.6

South Bridge

Aptio Setup Utility - Copyright (C) 2010 American Megatrends, Inc.

Advanced

Enabled/disabled the High

Precision Event Timer.

SB Chipset Configuration

High Precision Event Timer Configuration

High Precision Timer

[Enabled]

High Precision Timer [Enabled]

Allows you to enable or disable the High Precision Event Timer.

Configuration options: [Enabled] [Disabled]

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This manual is related to the following products:

PI4