Analog Devices SHARC Processors 82-003536-01 - Manual (Page 111)

Getting Started With SHARC Processors I-3
Index
Help system
described, 3-14
for VisualDSP++, 2-9
High-performance USB 2.0 JTAG
emulator (HPUSB), 2-55
HP-USB (high-performance USB JTAG
emulator), 2-55
I
IBIS (I/O buffer information specification)
defined, 3-8
models, 3-8
IDDE (integrated software development
and debugging environment), 2-2
instruction set reference, 3-6
integrated software development and
debugging environment. See IDDE
I/O buffer information specification. See
IBIS
J
Joint Test Action Group. See JTAG
JTAG emulators
defined, 2-54
USB 1.1, 2-58
USB 2.0, 2-55
JTAG (Joint Test Action Group), 2-54
K
Kaztek Engineering, courses provided, 3-5
kernel. See VDK
L
licenses
described, 2-13
floating, 2-61
linker description file, 3-11
loader, 3-11 , 3-12
M
manual
new in this edition, x
manuals. See documentation
MyAnalog.com
defined, xii
e-mail notifications for, xii
O
online Help. See Help system
operating systems, supporting VisualDSP,
2-4
P
PGO (profile-guided optimization), 2-8
processors
anomalies lists, 3-7
data sheets, 3-7
selection charts, 3-2
processor specifications
ADSP-2126x, 1-9
ADSP-2136x/ADSP-2137x, 1-10
ADSP-2146x, 1-11
ADSP-2147x, 1-13
ADSP-2187x, 1-15
processor support options, 3-1
Analog Devices Web site, 3-1
application notes, EE-Notes, 3-3
documentation, 3-5
EngineerZone, 3-15
LinkedIn, 3-16
SHARC processor web page, 3-2
third-party developers, 3-15
Twitter, 3-16
profile-guided optimization. See PGO