Advantech RISC Module SOM-A2552 - Manual (Page 25)

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User’s Manual for Advantech SOM-A2552 series module V1.00
25
Sync input of the LCD panel. For
STN displays, this output connects
to the Frame Clock input of the
LCD panel.
This output indicates the start of a
new frame of pixels. The panel
needs to reset its line pointers to
the top of the screen.
197 LP_HSYNC O Flat Panel TFT Vertical Sync/STN
Frame Pulse. For TFT displays,
this output connects to the Vertical
Sync input of the LCD panel. For
STN displays, this output connects
to the Frame Clock input of the
LCD panel.
This output indicates the start of a
new frame of pixels. The panel
needs to reset its line pointers to
the top of the screen.
No pulling
198 GND P Ground -
199 M_DE O Flat Panel Display Enable. This
signal is used as a data enable
when the pixel clock needs to latch
pixel data.
No pulling
200 SHCLK O Flat Panel Pixel Clock. The active
edge of FPCLK is programmable.
The LCD panel uses this clock
when loading pixel data into its
Line Shift register. This signal
connects to the TXCLK input of the
LVDS transmitter.
No pulling
¦100-pin B2B connector Pin Out Table (X1 connector, For AMI
interface)
Pin
No.
Signals Type Description
Default
state
B1 nBUF_CS2 O
Static chip selects. Chip selects to
static memory devices such as ROM
and Flash. Individually
programmable in the memory
configuration registers. This pin can
be used with variable latency I/O
devices. nBUF_CS2 directly connect
to SoC PXA255 nCS2. User could
use this pin as chip select pin to
control the solution IC on carrier
board. This pin is reserved for user
to use.
Pull-high
with 100K
ohm