Advantech RISC Module SOM-A2552 - Manual (Page 36)

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User’s Manual for Advantech SOM-A2552 series module V1.00
36
of the next one. The state of
VPHSYNC
determines whether the current
capture
field is ODD (VPHREF is High on
the
active edge of VPVSYNC) or
EVEN
(VPHREF is Low on the active
edge of
VPVSYNC).
A50
VPCLK I
Pixel Clock. VPCLK is the
reference clock for data on the
ZV[31:0] video pixel bus. No pulling
2.2 function description
2.2.1 System Bus
System Bus includes PXA255 address bus, data bus, memory control
signals and GPIOs.
System Bus enters CSB by X1. In order to make sure that system bus
signals have perfect electrical waves, System Bus signals are driven by buffers
to enhance signals performance.
The buffers signals direction control is control by CPLD on SOM-A255x
module.
2.2.2 COM
SOM-A255x series (SOM-A2552, SOM-A2558, SOM-A255F) all support 5
x RS-232 ports: 3 full function (FF) RS-232 ports, 1x 2-wire (RX, TX) RS-232
and 1x 3-wire (RX, TX, RTS) RS-232 port. COM port function assignments are
as following:
Ø COM1: FF RS-232
Ø COM2: FF RS-232
Ø COM3: FF RS-232
Ø COM4: 2-wire (RX, TX) RS-232
Ø COM5: 3-wire (RX, TX, RTS) RS-232
All RS-232 ports are TTL levels.