Analog Devices AD9843A - Manual (Page 7)

AD9843A
–7– REV. 0
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to
the peak deviation of the output of the AD9843A from a true
straight line. The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined
as a Level 1, 1/2 LSB beyond the last code transition. The devia-
tion is measured from the middle of each particular output
code to the true straight line. The error is then expressed as a
percentage of the 2 V ADC full-scale signal. The input signal is
always appropriately gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N codes) when N is the bit resolution of the
ADC. For the AD9843A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9843A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9843A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330 ⍀
DVDD
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DVSS DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Outputs
ACVDD
ACVSS ACVSS
Figure 3. CCDIN (Pin 30)
330 ⍀
DVDD DVDD
DVSS
DATA IN
RNW
DATA OUT
DVSS DVSS
Figure 4. SDATA (Pin 47)