Agilent Technologies Logic DDR2 Dimm High Speed Pro FS2334 - Manual (Page 20)

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The process for setting sampling positions at speeds of 800MT/s:
This procedure requires the probe user to capture TimingZoom traces and use the
markers to determine the correct sampling positions. This is an iterative, trial and error
procedure where adjustments to Data signal sampling positions may need to be
adjusted several times before they provide correct State data capture on both Read and
Writes.
When operating at 800MT/s data speed and a Multi-Frame configuration. There are
several things to consider:
1) There are 4 sets of State Data. These are:
a. Write Data sampled on the rising edge of CK0 Data63-0_R
b. Write Data sampled on the falling edge of CK0 Data63-0_F
c. Read Data sampled on the rising edge of CK2 READdata63-0_R
d. Read Data sampled on the falling edge of CK2 READdata63-0_F
2) Please note within each of these 4 groups of labels there are additional labels
organized by data byte. This is because many platforms may display timing
differences between byte groups and therefore require a slightly different sampling
setting which the byte labels make easier to both measure and set.
3) At 400MHz clock speed the 16900 analyzer in this configuration will display both the
State and TimingZoom version of the State Clock signal, (CommandClk) CK0 for the
Write analyzer and CK2 for the Read analyzer, at ½ it’s actual frequency. For an
.actual representation of the state clock use Write – Command:CK2_TZ
4) Because of the logic analyzer’s pod to pod skew of +/- 1.75ns, you want to take
several timing offset measurements before setting a sampling value.
5) Both the Write and Read analyzers are clocked only on the rising edge of their State
Clocks.
6) The Intermodule Skew should not need adjustment for State analysis. This can
done if necessary by aligning the MRAS_TZ (Write analyzer) and RAS_TZ (Read
analyzer) signals, but the user will have to reset it after every trace capture.
7) Sample positions for Command, Address and Control signals are already set to
values that should allow proper State analysis. If adjustment is necessary they can
be moved using either the TimingZoom measurement procedure described here, or
by using Auto Sample positioning provided that Chip Select qualification is applied
or the system is slowed down to a DDR clock rate of 333MHz and the logic analyzer
is set to 300MHz State mode.