Cirrus Logic CS1631 - Manual (Page 23)

CS1630/31
DS954F3 23
5.10.4 Register Lockout
The CS1630/31 provides register lockout for security against
unauthorized access to proprietary registers using the I
2 C or
PLC communication port. A 32-bit long-word is used for
password protection when accessing the OTP registers. The
register lockout password can be set by programming the
Lockout Key registers (see "Lockout Key (LOCK0, LOCK1,
LOCK2, LOCK3) – Address 1 - 4" on page 29). Register
lockout is enabled by setting bit LOCKOUT in register Config0
(see "Configuration 0 (Config0) – Address 0" on page 29).
5.11 I
2
C ™ Communication Interface
The purpose of the communication system is to provide a
mechanism to allow the transfer of data and accessibility to
the device. Pins SDA and SCL are an I
2 C communication port
used to provide access to control registers inside the EXL
core. In applications that do not use I
2 C communication, pins
SDA and SCL should be connected to VDD. When SDA and
SCL are connected to VDD, read/write register values are
controlled internally by the EXL core.
A one-time programmable (OTP) memory is implemented as
part of the communication system to store trim and key
parameters. After power-on reset (POR), the OTP memory is
uploaded into shadow registers as part of startup, and a cyclic
redundancy check (CRC) is calculated and checked on the
data read from the OTP memory. If the computed CRC does
not match the CRC value saved in the OTP memory, default
values are used for some of the parameters. Shadow registers
can be written using the I
2 C interface. In order to write to or
read from the I 2 C port, a defined messaging protocol must be
implemented.
The OTP memory is organized as 128 addressable bytes (8
bits). The contents of the OTP memory are read at reset and
are addressable by the I
2 C interface. The shadow register
values are used to control the internal operational parameters
of the IC and can be modified. However, in the event of a POR
or any kind of reset, the shadow registers will be rewritten with
the OTP memory content. In the event that a CRC verification
fails during normal operation, the registers will be rewritten
with OTP memory content, negating any changes that have
been made to the shadow registers.
The CRC is verified after the OTP memory has been uploaded
at POR, periodically during the operation of the IC, and at the
exit of Control Port mode. The CRC can be disabled by writing
to the CRC disable register, or by enabling the Control Port
mode (see "Control Port Enable" on page 24). The shadow
registers will be restored from OTP memory on a POR event,
or any reset type event. The CRC is calculated using
Equation 11.
The CRC calculation is implemented in hardware using a
linear feedback shift register starting with address 0 and
ending with address 57 (see Figure 26). The current CRC is
stored in address 63.
Figure 26. CRC Hardware Representation
To perform a successful write to the OTP memory, the CRC
must be calculated and stored in the CRC registers prior to
issuing the OTP write command. OTP memory can only be
written once. OTP shadow registers accessible to the user are
described in "One-Time Programmable (OTP) Registers" on
page 27.
5.11.1 I
2
C Control Port Protocol
The communication port is designed to allow a master device
to read and write the OTP shadow registers of the CS1630/31
and the capability of programming the OTP memory using the
data in the shadow registers. The OTP shadow registers
provide a mechanism for configuring the device and
calibrating the system prior to programming the device. The
CS1630/31 communication port physical layer adheres to the
I
2 C bus specification by Philips Semiconductor version 2.1,
January 2000 (see "I 2 C™ Port Switching Characteristics" on
page 8). The CS1630/31 control port only supports I 2 C slave
functionality. The CS1630/31 I 2 C interface is intended for use
with a single master and no other slaves on the bus.
Figure 27 illustrates the frame format used for I
2 C data
transfers. The first bit is a Start condition (bit S) followed by an
8-bit slave address that is comprised of a 7-bit device address
plus a Read/Write (R/W) bit. The R/W bit is the least
significant bit of the slave address byte, which indicates
CRC CRC x
8
x
2
x 1 + + +    = [Eq.11]
0 1 2 3 8
Figure 27. I 2 C Frame Format
‘1’ = Block
‘0’ = Single
P A Data S A A
Device Address
(7-bit)
Register Address
(7-Bit)
Data
… ...
From Slave to Master
From Master to Slave
BLK/SGL R/ W
‘1’ = Read
‘0’ = Write
Start
Condition
Stop
Condition
‘A’ = Acknowledge (SDA Low)
A = Not Acknowledge (SDA High) ‘ ’
A/A A/A
Data Transferred
(n bytes and acknowledge)
A/A A/A
Slave Address
(1 byte and acknowledge)