Cirrus Logic CS1631 - Manual (Page 7)

CS1630/31
DS954F3 7
Notes: 1. The CS1630/31 has an internal shunt regulator that limits the voltage on the VDD pin. V
Z
, the shunt regulation voltage, is defined
in the VDD Supply Voltage section on page 6.
2. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.
3. Conductance is the inverse of resistance (1/ ) and is expressed in siemens (S). A decrease in conductance is equivalent to an
increase in resistance.
4. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.
5. For test purposes, load capacitance (C
L
) is 0.25nF and is connected as shown in the following diagram.
Second Stage Pulse Width Modulator
Minimum Switching Frequency
t
FB(Min)
- 625 - Hz
Maximum Switching Frequency t
FB(Max)
- 200 - kHz
Second Stage Gate Driver
Output Source Resistance
V
DD
= 12V - 24 - 
Output Sink Resistance V
DD
= 12V - 11 - 
Rise Time (Note 5) C
L
= 0.25nF - - 30 ns
Fall Time (Note 5) C
L
= 0.25nF - - 20 ns
Second Stage Protection
Overcurrent Protection (OCP)
V
OCP(th)
- 1.69 - V
Overvoltage Protection (OVP) V
OVP(th)
- 1.25 - V
Open Loop Protection (OLP) V
OLP(th)
- 200 - mV
External Overtemperature Protection (eOTP)
Pull-up Current Source – Maximum
I
CONNECT
- 80 - A
Conductance Accuracy (Note 3) - - ±5 
Conductance Offset (Note 3) - ±250 - nS
Current Source Voltage Threshold V
CONNECT(th)
- 1.25 - V
Internal Overtemperature Protection (iOTP)
Thermal Shutdown Threshold
(Note 4) T
SD
- 135 - ºC
Thermal Shutdown Hysteresis (Note 4) T
SD(Hy)
- 14 - ºC
Parameter Condition Symbol Min Typ Max Unit
GD OUT
GD
GND
VDD
Buffer
S
1
R
1
R
2
R
3
TP
+15V
-15V
S
2
V
DD
C
L
0.25nF