3 freeze (bit 2), 4 control port enable (bit 1), 5 power down (bit 0) – Cirrus Logic CS4272 User Manual

Page 44: 8 chip id - register 08h, 1 chip id (bits 7:4), 2 chip revision (bits 3:0), Cs4272

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3 freeze (bit 2), 4 control port enable (bit 1), 5 power down (bit 0) | 8 chip id - register 08h, 1 chip id (bits 7:4), 2 chip revision (bits 3:0), Cs4272 | Cirrus Logic CS4272 User Manual | Page 44 / 53 3 freeze (bit 2), 4 control port enable (bit 1), 5 power down (bit 0) | 8 chip id - register 08h, 1 chip id (bits 7:4), 2 chip revision (bits 3:0), Cs4272 | Cirrus Logic CS4272 User Manual | Page 44 / 53
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