Cirrus Logic CS43L21 - Manual (Page 4)

4 DS723F1
CS43L21
6.2 Power Control 1 (Address 02h) ...................................................................................................... 40
6.3 Speed Control (Address 03h) ......................................................................................................... 41
6.4 Interface Control (Address 04h) ..................................................................................................... 42
6.5 DAC Output Control (Address 08h) ................................................................................................ 42
6.6 DAC Control (Address 09h) ............................................................................................................ 43
6.7 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 45
6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 46
6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46
6.10 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 48
6.11 Tone Control (Address 15h) ......................................................................................................... 49
6.12 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49
6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 50
6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 51
6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 52
6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 53
6.17 Status (Address 20h) (Read Only) ............................................................................................... 53
6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 54
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 55
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 55
7.2 Headphone Amplifier Efficiency ...................................................................................................... 57
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 58
8.1 Auto Detect Enabled ....................................................................................................................... 58
8.2 Auto Detect Disabled ...................................................................................................................... 59
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 60
9.1 Power Supply, Grounding ............................................................................................................... 60
9.2 QFN Thermal Pad .......................................................................................................................... 60
10. DIGITAL FILTERS .............................................................................................................................. 61
11. PARAMETER DEFINITIONS .............................................................................................................. 62
12. REFERENCES .................................................................................................................................... 62
13. PACKAGE DIMENSIONS ............................................................................................................. 63
THERMAL CHARACTERISTICS .......................................................................................................... 63
14. ORDERING INFORMATION ............................................................................................................. 64
15. REVISION HISTORY ......................................................................................................................... 64
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10
Figure 3.Headphone Output Test Load ..................................................................................................... 15
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17
Figure 6.Control Port Timing - I²C ............................................................................................................. 18
Figure 7.Control Port Timing - SPI Format ................................................................................................ 19
Figure 8.Output Architecture ..................................................................................................................... 24
Figure 9.De-Emphasis Curve .................................................................................................................... 25
Figure 10.Beep Configuration Options ...................................................................................................... 26
Figure 11.Peak Detect & Limiter ............................................................................................................... 27
Figure 12.Master Mode Timing ................................................................................................................. 29
Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30
Figure 14.I²S Format ................................................................................................................................. 30
Figure 15.Left-Justified Format ................................................................................................................. 31
Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31
Figure 17.Initialization Flow Chart ............................................................................................................. 33